MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 204

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
QCLK EXAMPLES
SYSTEM CLOCK
Example
Number
Figure 5-9
include conversion times based on the following assumption:
Figure 5-9
version in a queue. For other MCU system clock frequencies and other input sample
times, the same calculations can be made.
The MCU system clock frequency is the basis of the QADC64 timing. The QADC64
requires that the system clock frequency be at least twice the QCLK frequency. The
QCLK frequency is established by the combination of the PSH and PSL parameters in
QACR0. The 5-bit PSH field selects the number of system clock cycles in the high
phase of the QCLK wave. The 3-bit PSL field selects the number of system clock
cycles in the low phase of the QCLK wave.
Example 1 in
twelve cycles of the system clock. It also shows that when PSL = 7, the QCLK remains
low for eight system clock cycles. In example 2, PSH = 7, the QCLK remains high for
eight cycles of the system clock. It also shows that when PSL = 7, the QCLK remains
low for eight system clock cycles.
1
2
1. 40 MHz
2. 32 MHz
• Input sample time is as fast as possible (IST = 0, 2 QCLK cycles).
F
SYS
Frequency
PSA is maintained for software compatibility but has no functional
benefit to this version of the module.
40 Mhz
32 Mhz
and
and
Figure 5-9 QADC64 Clock Programmability Examples
Control Register 0 Information
Figure 5-9
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Table 5-4
Table 5-4
Table 5-4 QADC64 Clock Programmability
Freescale Semiconductor, Inc.
For More Information On This Product,
PSH
11
7
also show the conversion time calculated for a single con-
shows that when PSH = 11, the QCLK remains high for
show examples of QCLK programmability. The examples
Go to: www.freescale.com
Rev. 25 June 03
PSA
0
0
NOTE
20 CYCLES
PSL
7
7
Input Sample Time (IST) = 0b00
QCLK
(MHz)
2.0
2.0
Conversion Time
MOTOROLA
( s)
7.0
7.0
QADC64 QCLK EX
5-28