MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 27

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor, Inc.
Page
Table
Number
Number
6-3 QSMCMMCR Bit Settings...................................................................................... 6-7
6-4 QILR Bit Settings ................................................................................................... 6-8
6-5 QIVR Bit Settings................................................................................................... 6-8
6-6 QSPI_IL Bit Settings .............................................................................................. 6-8
6-7 QSMCM Pin Control Registers .............................................................................. 6-9
6-8 Effect of DDRQS on QSPI Pin Function .............................................................. 6-10
6-9 QSMCM Pin Functions ........................................................................................ 6-11
6-10 PQSPAR Bit Settings......................................................................................... 6-12
6-11 DDRQS Bit Settings........................................................................................... 6-13
6-12 QSPI Register Map............................................................................................ 6-16
6-13 SPCR0 Bit Settings........................................................................................... 6-17
6-14 Bits Per Transfer................................................................................................ 6-17
6-15 SPCR1 Bit Settings........................................................................................... 6-18
6-16 SPCR2 Bit Settings........................................................................................... 6-19
6-17 SPCR3 Bit Settings........................................................................................... 6-20
6-18 SPSR Bit Settings............................................................................................. 6-21
6-19 Command RAM Bit Settings ............................................................................. 6-23
6-20 QSPI Pin Functions ........................................................................................... 6-24
6-21 Example SCK Frequencies
with a 40-MHz System Clock ........................................................................ 6-35
6-22 SCI Registers..................................................................................................... 6-44
6-23 SCCxR0 Bit Settings......................................................................................... 6-45
6-24 SCCxR1 Bit Settings......................................................................................... 6-46
6-25 SCxSR Bit Settings........................................................................................... 6-48
6-26 SCxSR Bit Settings........................................................................................... 6-50
6-27 SCI Pin Functions .............................................................................................. 6-50
6-28 Serial Frame Formats ........................................................................................ 6-51
6-29 Examples of SCIx Baud Rates .......................................................................... 6-52
6-30 Effect of Parity Checking on Data Size.............................................................. 6-52
6-31 QSCI1CR Bit Settings....................................................................................... 6-57
6-32 QSCI1SR Bit Settings....................................................................................... 6-59
7-1 Common Extended/Standard Format Frames....................................................... 7-5
7-2 Message Buffer Codes for Receive Buffers........................................................... 7-5
7-3 Message Buffer Codes for Transmit Buffers.......................................................... 7-5
7-4 Extended Format Frames ...................................................................................... 7-6
7-5 Standard Format Frames....................................................................................... 7-6
7-6 Receive Mask Register Bit Values......................................................................... 7-8
7-7 Mask Examples for Normal/Extended Messages .................................................. 7-8
7-8 Example System Clock, CAN Bit Rate and S-Clock Frequencies ......................... 7-9
7-9 Interrupt Sources and Vector Addresses............................................................. 7-20
7-10 TouCAN Register Map....................................................................................... 7-22
7-11 TCNMCR Bit Settings ....................................................................................... 7-24
7-12 CANICR Bit Settings......................................................................................... 7-26
7-13 CANCTRL0 Bit Settings.................................................................................... 7-26
7-14 RX MODE[1:0] Configuration............................................................................. 7-27
MC68F375
LIST OF TABLES
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
xxvii
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