MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 80

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.10.10 Recommended BDM Connection
3.10.11 Deterministic Opcode Tracking
MC68F375
REFERENCE MANUAL
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however, Motorola reserves the right to
use this bit for future enhancements.
In order to provide for use of development tools when an MCU is installed in a system,
Motorola recommends that appropriate signal lines be routed to a male Berg connec-
tor or double-row header installed on the circuit board with the MCU. Refer to
3-12.
CPU32 function code outputs are augmented by two supplementary signals to monitor
the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each
new instruction and each mid-instruction pipeline advance. The instruction fetch
(IFETCH) output identifies the bus cycles in which the operand is loaded into the
S/C
STATUS CONTROL BIT
16
15
Bit 16
0
0
1
1
1
Table 3-7 CPU Generated Message Encoding
Freescale Semiconductor, Inc.
Figure 3-12 BDM Connector Pinout
For More Information On This Product,
Figure 3-11 BDM Serial Data Word
XXXX
FFFF
FFFF
0000
0001
Data
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
RESET
GND
GND
V DD
DS
Rev. 25 June 03
BERR terminated bus cycle; Data invalid
Not ready with response; Come again
1
3
5
7
9
Command complete; Status OK
DATA FIELD
10
2
4
6
8
Valid data transfer
Illegal command
Message Type
BERR
BKPT/DSCLK
FREEZE
IFETCH/DSI
IPIPE/DSO
BDM SERIAL DATA WORD
0
MOTOROLA
32 BERG
Figure
3-26