MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 293

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.9.3 QSCI1 Transmitter Block Diagram
MC68F375
REFERENCE MANUAL
Bit(s)
15:13
7:4
3:0
12
11
10
9
8
The block diagram of the enhancements to the SCI transmitter is shown in
12.
QPEND
QRPNT
QBHF
QTHE
QBHE
Name
QTHF
QOR
—
Reserved
Receiver queue overrun error. The QOR is set when a new data frame is ready to be transferred
from the SC1DR to the queue and the queue is already full (QTHF or QBHF are still set). Data
transfer is inhibited until QOR is cleared. Previous data transferred to the queue remains valid.
Additional data received during a queue overrun condition is not lost provided the receive queue
is re-enabled before OR (SC1SR) is set. The OR flag is set when a new data frame is received
in the shifter but the data register (SC1DR) is still full. The data in the shifter that generated the
OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost.
0 = The queue is empty before valid data is in the SC1DR
1 = The queue is not empty when valid data is in the SC1DR
Receiver queue top-half full. QTHF is set when the receive queue locations SCRQ[0:7] are com-
pletely filled with new data received via the serial shifter. QTHF is cleared when register
QSCI1SR is read with QTHF set, followed by a write of QTHF to zero.
0 = The queue locations SCRQ[0:7] are partially filled with newly received data or is empty
1 = The queue locations SCRQ[0:7] are completely full of newly received data
Receiver queue bottom-half full. QBHF is set when the receive queue locations SCRQ[8:15] are
completely filled with new data received via the serial shifter. QBHF is cleared when register
QSCI1SR is read with QBHF set, followed by a write of QBHF to zero.
0 = The queue locations SCRQ[8:15] are partially filled with newly received data or is empty
1 = The queue locations SCRQ[8:15] are completely full of newly received data
Transmitter queue top-half empty. QTHE is set when all the data frames in the transmit queue
locations SCTQ[0:7] have been transferred to the transmit serial shifter. QTHE is cleared when
register QSCI1SR is read with QTHE set, followed by a write of QTHE to zero.
0 = The queue locations SCTQ[0:7] still contain data to be sent to the transmit serial shifter
1 = New data may now be written to the queue locations SCTQ[0:7]
Transmitter queue bottom-half empty. QBHE is set when all the data frames in the transmit
queue locations SCTQ[8:15] has been transferred to the transmit serial shifter. QBHE is cleared
when register QSCI1SR is read with QBHE set, followed by a write of QBHE to zero.
0 = The queue locations SCTQ[8:15] still contain data to be sent to the transmit serial shifter
1 = New data may now be written to the queue locations SCTQ[8:15]
Queue receive pointer. QRPNT is a 4-bit counter used to indicate the position where the next
valid data frame will be stored within the receive queue. This field is writable in test mode only;
otherwise it is read-only.
Queue pending. QPEND is a 4-bit decrementer used to indicate the number of data frames in
the queue that are awaiting transfer to the SC1DR. This field is writable in test mode only; other-
wise it is read-only. From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can
be specified.
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Table 6-32 QSCI1SR Bit Settings
Go to: www.freescale.com
Rev. 25 June 03
Description
MOTOROLA
Figure 6-
6-59