MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 89

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.3.2 Clock Synthesizer Submodule
MC68F375
REFERENCE MANUAL
has a defined relationship to f
reset.
The MC68F375 contains an improved version of the clock synthesizer subsystem. The
new architecture accommodates both slow or fast crystal references, see
tem Clock
consideration when this new architecture was defined. Compatibility with the previous
architecture has been retained when possible.
In general, the improvements fall into four basic categories as follows:
There are three modes for generating the system clock for the MCU. The system clock
may be driven directly into the EXTAL pin (external clock mode), it may be generated
on-chip by a phase locked loop (PLL) frequency synthesizer using either a slow or fast
reference mode. For modes using the PLL, a lock detect circuit detects that the PLL is
on frequency and sets a register flag. The PLL mode is determined at reset and
behaves according to
by the state of the FASTREF/PF0 and V
mode, the V
The MC68F375’s clock architecture supports the three modes of operation by option-
ally reconfiguring the number and location of the W bit and Y bit divider stages. In slow
reference mode, one W bit and six Y bits are located in the PLL feedback path,
enabling frequency multiplication by a factor of up to 2048. The X bit is located in the
VCO clock output path to enable dividing the system clock frequency by two without
disturbing the VCO and thus requiring re-lock. In fast reference mode, three W bits are
located in the PLL feedback path, enabling frequency multiplication by a factor from 1
to 8. Three Y bits and the X bit are located in the VCO clock output path to provide the
ability to slow the system clock without disturbing the PLL. In external clock mode,
three Y bits and the X bit are located between the EXTAL input and the system clock,
to allow slowing the clock for reduced power consumption. Refer to
4-3, and
value of the W, X and Y bits are determined by the clock mode as shown in
• Configurable PLL for optimization of divider chain based on mode of operation;
• Improved loss-of-clock circuitry based on an independent RC oscillator;
• Improved lock detect circuitry;
• Improved noise immunity by the addition of a V
Figure 4-2
The crystal oscillator and frequency synthesizer circuits are powered
from a separate power pin pair (V
oscillator to continue to run when the rest of the chip is powered
down. This allows avoidance of crystal start-up time. Separate sup-
plies also help improve noise immunity.
Sources. Range of operation and power consumption were taken into
DDSYN
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
/MODCK pin must be tied directly to V
Freescale Semiconductor, Inc.
for block diagrams of the architecture in these modes. The reset
Table
For More Information On This Product,
4-5. The source of the system clock is determined at reset
Go to: www.freescale.com
REF
Rev. 25 June 03
that depends on the clock mode selected during
DDSYN
NOTE
DDSYN
/MODCK pins. To enable external clock
SSSYN
and V
SS
SSSYN
pin.
at all times
) to allow the
Figure
4-4,
MOTOROLA
4.3.1 Sys-
Table
Figure
4-6.
4-7