MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 269

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.5.3 Delay Before Transfer
6.7.5.4 Delay After Transfer
MC68F375
REFERENCE MANUAL
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled
and assumes its inactive state. At reset, the SCK baud rate is initialized to one eighth
of the system clock frequency.
Table 6-21
The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or
user-specified (DSCK = 1) delay from chip-select assertion until the leading edge of
the serial clock. The DSCKL field in SPCR1 determines the length of the user-defined
delay before the assertion of SCK. The following expression determines the actual
delay before SCK:
When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transi-
tion is one-half the SCK period.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. Writing a value to the DTL field in SPCR1 specifies a delay period.
The DT bit in each command RAM byte determines whether the standard delay period
where DSCKL is in the range from 1 to 127.
A zero value for DSCKL causes a delay of 128 system clocks, which
equals 3.2 µs for a 40-MHz system clock. Because of design limits,
a DSCKL value of one defaults to the same timing as a value of two.
provides some example SCK baud rates with a 40-MHz system clock.
Freescale Semiconductor, Inc.
Table 6-21 Example SCK Frequencies
QUEUED SERIAL MULTI-CHANNEL MODULE
Division Ratio
For More Information On This Product,
with a 40-MHz System Clock
280
510
PCS to SCK Delay =
14
28
58
4
6
8
Go to: www.freescale.com
Rev. 25 June 03
SPBR Value
140
255
14
29
2
3
4
7
NOTE
Frequency
10.00 MHz
78.43 kHz
6.67 MHz
5.00 MHz
2.86 MHz
1.43 MHz
689 kHz
143 kHz
DSCKL
f
SCK
SYS
MOTOROLA
6-35