MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 458

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.5.2.6 Output Pulse Width Modulation (OPWM) Mode
MC68F375
REFERENCE MANUAL
OPWM mode is selected by making MODE[3:0] = 1xxx. The MODE[2:0] bits allow
some of the comparator bits to be masked.
This mode allows pulse width modulated output waveforms to be generated, with eight
selectable frequencies (for a given time base). Both channels (A and B) are used to
generate one PWM output signal on the DASM pin.
Channel B is accessed via register B1. Register B2 is not accessible to the user. Chan-
nels A and B define the leading and trailing edges, respectively, of the PWM output
pulse. The value in register B1 is continuously transferred to register B2 in the time
between each trailing edge and the following leading edge.
The value loaded in register A is continuously compared with the value on the time
base bus. When a match on A occurs, the FLAG bit is set and the output flip-flop is set.
The value loaded in register B2 is continually compared with the value on the time
base bus. When a match occurs on B, the output flip-flop is reset.
The polarity of the PWM output signal is selected by the EDPOL bit. The output flip-
flop level can be obtained at any time by reading the IN bit.
If subsequent compares occur on channels A and B, the PWM pulses continue to be
output, regardless of the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-
flop to the level corresponding to comparison on A or B respectively. Note that the
FLAG bit is not affected by the FORCA and FORCB operations.
If both channels are loaded with the same value they will try to force different levels on
the output flip-flop. Hardware protection circuitry ensures that no contention occurs
and the output flip-flop provides a logic zero level output.
Figure 13-12
modulation.
There is no hardware protection to disable comparator B while com-
parator A is enabled. It is the user’s responsibility to load data
registers A and B with the values needed to produce the desired
PWM output pulse.
provides an example of how the DASM can be used for pulse width
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
Rev. 25 June 03
WARNING
MOTOROLA
13-32