MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 516

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
A new feature of the TPU3 microcode ROM is the existence of two entry tables in the
4 Kbytes of internal ROM. Each entry table has a set of sixteen functions and the user
defines which of the two tables the TPU3 will be able to access. Only one table can be
used at a time and functions from the two entry tables cannot be mixed. The default
entry table is located in bank zero. This table is identical to the standard microcode
ROM in the TPU2, so any CPU code written for the TPU2 will work unchanged on the
TPU3. The functions in the default entry table in bank zero are listed in Table 1.
The CPU selects which entry table to use by setting the ETBANK field in the
TPUMCR2 register. This register is write once after reset. Although one entry table is
specified at start-up, it is possible, in some cases, to use functions from both
tables without resetting the microcontroller. A customer may, for example, wish to use
the ID function from bank one to verify the TPU microcode version but then use the
MCPWM function from bank zero. As a customer will typically only run the ID function
during system configuration, and not again after that, the bank one entry table can be
changed to the bank zero entry table using the soft reset feature of the TPU3. The pro-
cedure should be:
The TPU3 stays in reset until the CPU clears the SOFTRST bit. After the SOFTRST
bit has been cleared the TPU3 will be reset and the entry table in bank zero will be
1. Set ETBANK field in TPUMCR2 to %01 to select the entry table in bank one
2. Run the ID function
3. Stop the TPU3 by setting the STOP bit in the TPUMCR to one.
4. Reset the TPU3 by setting the SOFTRST bit in the TPUMCR2 register
5. Wait at least nine clocks
6. Clear the SOFTRST bit in the TPUMCR2 register
Function Number
$D
$C
$F
$E
$B
$A
9
8
7
6
5
4
3
2
1
0
Freescale Semiconductor, Inc.
For More Information On This Product,
Nickname
MCPWM
Function
HALLD
COMM
SPWM
PPWA
UART
PWM
SIOP
QOM
NITC
FQM
TSM
FQD
PTA
DIO
Table D-1 Bank 0 Functions
OC
Go to: www.freescale.com
TPU ROM FUNCTIONS
Rev. 25 June 03
Programmable Time Accumulator
Queued Output Match
Table Stepper Motor
Frequency Measurement
Universal Asynchronous Receiver/Transmitter
New Input Capture/Input Transition Counter
Multiphase Motor Commutation
Hall Effect Decode
Multi-Channel Pulse Width Modulation
Fast Quadrature Decode
Period/Pulse Width Accumulator
Output Compare
Pulse Width Modulation
Discrete Input/Output
Synchronized Pulse Width Modulation
Serial Input/output Port
Function Name
MOTOROLA
D-2