MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 170

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.10.1 Ports A and B
4.10.2 Port A and B Data Registers
PORTA — Port A Data Register
PORTB — Port B Data Register
4.10.3 Port E
MC68F375
REFERENCE MANUAL
MSB
PA7
15
U
RESET:
If emulation mode is enabled, accesses to the port A, B, F, G, and H data and data
direction registers and the port E pin assignment register are mapped externally, and
cause the CSE port emulation chip select to be asserted. The SCIM2E does not
respond to these accesses, but allows external logic, such as the Motorola
MC68HC33 port replacement unit (PRU), to respond. Accesses to the port F registers
will still be handled by the SCIM2E.
A write to the port A, B, E, F, G, or H data register is stored in the port’s internal data
latch. If any port pin is configured as an output, the value stored for that bit is driven
on the pin. A read of the port data register returns the value at the pin only if the pin is
configured as a discrete input. Otherwise, the value read is the value stored in the data
latch.
Ports A and B are available in single-chip mode only. One data direction register con-
trols the data direction for both ports. The SCIM2E will respond to port A and B
registers at any time the MCU is not in emulation mode.
The port A/B data direction bits (DDA and DDB) control the direction of the pin drivers
for ports A and B, respectively. Setting DDA or DDB to one configures all correspond-
ing port pins as outputs. Clearing DDA or DDB to zero configures all corresponding
port pins as inputs.
Ports A and B are available in single-chip mode only. PORTA and PORTB can be read
or written any time the MCU is not in emulator mode.
Port E can be made available in all operating modes. The state of BERR and DATA8
at the release of RESET controls whether the port E pins are initially configured as bus
control signals or discrete I/O lines.
If the MCU is in emulation mode, accesses to the port E data, data direction, and pin
assignment registers (PORTE, DDRE, and PEPAR) are mapped externally. This
allows port replacement logic to be supplied externally, giving an emulator access to
the bus control signals.
PA6
14
U
PA5
13
U
PA4
12
U
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
PA3
Freescale Semiconductor, Inc.
11
U
For More Information On This Product,
PA2
10
U
Go to: www.freescale.com
PA1
U
9
Rev. 25 June 03
PA0
U
8
PB7
U
7
PB6
U
6
PB5
U
5
PB4
U
4
PB3
U
3
PB2
U
2
0xYF FA0A
0xYF FA0B
MOTOROLA
PB1
U
1
LSB
PB0
U
0
4-88