MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 392

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.5 CMFI EEPROM Array Addressing
10.5.1 Read Burst Buffers
MC68F375
REFERENCE MANUAL
The base address of the memory block in which the CMFI EEPROM array resides is
specified in the array base address register (CMFIBAR). The default reset base
address is specified in the shadow registers by the user. The only restrictions on the
base address are that it must be on a 2
on array size). If the base address is set such that the CMFI EEPROM array overlaps
the control register block, accesses to the 32-bytes of the array that overlap the control
registers will be ignored, allowing the control block to remain accessible. This is only
true with respect to the same CMFI EEPROM module. If the control register blocks of
other modules are overlapped by the CMFI EEPROM array, accesses to the over-
lapped addresses will be indeterminate.
The CMFI EEPROM array is divided into a shadow row and eight 32-Kbyte blocks as
shown in
tion is stored in shadow block. The array supports multiple-page programming.
Information in the array is accessed in 32-byte burst buffers. Two read burst buffers
are aligned to the low order addresses (IADDR[4:0]). The first burst buffer is associ-
ated with the lower array blocks. The second burst buffer is associated with the higher
array blocks. Read access time from the array will take 2, 3, 4 or 5 clocks as defined
by WAIT[1:0] for the first data access. If a burst access the following access are 1 clock
accesses from within the 32-byte burst buffer. To prevent the BIU from unnecessarily
refreshing the burst buffer from the array, the CMFI EEPROM shall monitor the IMB3
address to determine if the required information is within one of the two read burst buff-
ers and the access is valid for the module.
Write accesses to the CMFI array will not assert the address acknowledge unless they
are programming or erase interlock writes.
The two 32-byte read burst buffers are fully independent and are located in two sepa-
rate read sections of the array as indicated in
and address are monitored in the BIU. The status of the read burst buffers are usually
valid, but are made invalid by the following operations:
3. Determine CLKPM:
4. Check the results:
• Setting/Clearing VT
nents in the range of N=6. While any of these values can be selected
CLKPE[0:1]=00, N=6, will be used for the example.
Using the selected values of N and R in the pulse width equation and solving
for M yields M=8.8. Rounding M to 9 then CLKPM[0:6]=0x8 (0b0001000).
Pulse Width=System Clock Period
using SCLKR[0:2]=100, CLKPE[0:1]=00, CLKPM[0:6]=0001000 and PE=0 at
33.0 MHz system clock. Pulse Width=30.3 µS • 3 • 2
pulse.
10.6.6.3 Programming Shadow
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
N
byte boundary (N = 16, 17 or 18 depending
•
Information. The shadow register informa-
R
•
2
Figure
N
•
M
10-1. Each burst buffer status
6
• 9=52.4 µS program
MOTOROLA
10-22