MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 87

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.2.5 Show Internal Cycles
4.2.6 FREEZE Assertion Response
MC68F375
REFERENCE MANUAL
EXOFF disables the CLKOUT external clock output pin by placing the pin in a high-
impedance state. CLKOUT is enabled at power-up unless explicitly disabled by writing
a zero to EXOFF.
CPUD disables the IPIPE/DSO and IFETCH/DSI instruction tracking pins by placing
them in a high-impedance state when the MCU is not in background debug mode
(BDM). When the MCU enters BDM and FREEZE is asserted, IPIPE/DSO and
IFETCH/DSI become active and serve as the BDM serial I/O lines.
ABD and RWD disable the ADDR[2:0] and R/W pins by placing them in a high-imped-
ance state. These pins should be disabled because they cannot be used for discrete
I/O and have no use in single-chip mode.
A show cycle allows internal bus transfers to be monitored externally. The SHEN field
in SCIMMCR determines what the external data bus interface does during internal
transfer operations.
external bus arbitration can occur. The external address bus is always driven. Refer to
4.6.6.1 Show Cycles
When the CPU32 enters background debug mode, the IMB FREEZE signal is
asserted. The FRZ[1:0] bits in SCIMMCR control the behavior of the software watch-
dog, periodic interrupt timer, and bus monitor in response to FREEZE assertion. By
default, these protection mechanisms are disabled in BDM; they can be selectively
enabled by the FRZ[1:0] bits as shown in
0
0
1
1
SHEN[1:0]
FRZ[1:0]
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
00
01
10
11
Freescale Semiconductor, Inc.
Table 4-4 Effects of FREEZE Assertion
Table 4-3
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for more information.
Table 4-3 Show Cycle Enable Bits
0
1
0
1
Show cycles disabled, external arbitration enabled
Show cycles enabled, external arbitration disabled
Show cycles enabled, external arbitration enabled
Show cycles enabled, external arbitration enabled;
internal activity is halted by a bus grant
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shows whether data is driven externally, and whether
None
Bus monitor
Software watchdog and periodic interrupt timer
Both
Rev. 25 June 03
Table
Disabled Elements
Effect
4-4.
MOTOROLA
4-5