MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 368

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MISCNT — MISC Counter
9.4.5 MISC Counter (MISCNT)
9.5 Operation
9.5.1 Normal Operation
9.5.2 Standby Operation
9.5.3 Reset Operation
MC68F375
REFERENCE MANUAL
MSB
A12
15
RESET:
The MISCNT contains the address of the current MISC memory access. This registers
is read-only. Note that the naming of the A[31:0] bits represents little-endian bit
encoding.
Exiting TPU3 emulation mode or clearing the MISEN bit in the DPTMCR results in the
reset of this register.
The DPTRAM module has several modes of operation. The following sections
describe DPTRAM operation in each of these modes.
In normal operation, the DPTRAM is powered by V
IMB3 by a bus master.
Read or write accesses of 8, 16, or 32 bits are supported. In normal operation, neither
TPU3 accesses the array, nor do they have any effect on the operation of the
DPTRAM module.
The DPTRAM on the MC68F375 does not support standby operation. The
VDDDPTRAM should always be powered up and down with VDDL.
When a synchronous reset occurs, a bus master is allowed to complete the current
access. Thus a write bus cycle (byte or half word) that is in progress when a synchro-
nous reset occurs will be completed without error. Once a write already in progress
has been completed, further writes to the RAM array are inhibited.
A11
14
A10
13
A9
12
Freescale Semiconductor, Inc.
A8
11
For More Information On This Product,
10
A7
DUAL-PORT TPU RAM (DPTRAM)
Go to: www.freescale.com
A6
9
Last Memory Address
Rev. 25 June 03
A5
8
A4
7
A3
6
DDL
A2
5
and may be accessed via the
A1
4
A0
3
2
RESERVED
0xYF F88A
MOTOROLA
1
LSB
0
9-6