MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 239

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Access
6.5.1 Low-Power Stop Operation
6.5.2 Freeze Operation
6.5.3 Access Protection
MC68F375
REFERENCE MANUAL
NOTES:
1. S = Supervisor access only
2. 8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries.
S
S
S
T
When the STOP bit in QSMCMMCR is set, the system clock input to the QSMCM is
disabled and the module enters a low-power operating state. QSMCMMCR is the only
register guaranteed to be readable while STOP is asserted. The QSPI RAM is not
readable in low-power stop mode. However, writes to RAM or any register are guar-
anteed valid while STOP is asserted. STOP can be written by the CPU and is cleared
by reset.
System software must bring each submodule to an orderly stop before setting STOP
to avoid data corruption. The SCI receiver and transmitter should be disabled after
transfers in progress are complete. The QSPI can be halted by setting the HALT bit in
SPCR3 and then setting STOP after the HALTA flag is set.
The FRZ1 bit in QSMCMMCR determines how the QSMCM responds when the IMB3
FREEZE signal is asserted. FREEZE is asserted when the CPU enters background
debug mode. Setting FRZ1 causes the QSPI to halt on the first transfer boundary fol-
lowing FREEZE assertion. FREEZE causes the SCI1 transmit queue to halt on the first
transfer boundary following FREEZE assertion.
The SUPV bit in the QMCR defines the assignable QSMCM registers as either super-
visor-only data space or unrestricted data space.
When the SUPV bit is set, all registers in the QSMCM are placed in supervisor-only
space. For any access from within user mode, the IMB3 address acknowledge (AACK)
signal is asserted and a bus error is generated.
Because the QSMCM contains a mix of supervisor and user registers, AACK is
asserted for either supervisor or user mode accesses, and the bus cycle remains inter-
nal. If a supervisor-only register is accessed in user mode, the module responds as if
an access had been made to an unauthorized register location, and a bus error is
generated.
S/U = Supervisor access only or unrestricted user access (assignable data space).
1
0xYF FC00
0xYF FC02
0xYF FC04
0xYF FC06
Address
MSB
Dual SCI Interrupt Level (QDSCI_IL)
2
Freescale Semiconductor, Inc.
See
QUEUED SERIAL MULTI-CHANNEL MODULE
Table 6-2 QSMCM Global Registers
For More Information On This Product,
Table 6-4
Reserved
QSMCM Module Configuration Register (QSMCMMCR)
Go to: www.freescale.com
for bit descriptions.
Rev. 25 June 03
See
QSMCM Test Register (QTEST)
Table 6-3
for bit descriptions.
QSM Interrupt Vector Register (QIVR)
Queued SPI Interrupt Level (QSPI_IL)
See
See
Table 6-5
Table 6-6
for bit descriptions.
for bit descriptions.
MOTOROLA
LSB
6-5