MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 60

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.2.3 Program Counter
3.2.4 Control Registers
3.2.4.1 Status Register
MC68F375
REFERENCE MANUAL
The PC contains the address of the next instruction to be executed by the CPU32.
During instruction execution and exception processing, the processor automatically
increments the contents of the PC or places a new value in the PC as appropriate.
The control registers described in this section contain control information for supervi-
sor functions and vary in size. With the exception of the condition code register (the
user portion of the status register), the control registers are accessed only by instruc-
tions at the supervisor privilege level.
The status register (SR) stores the processor status. It contains the condition codes
that reflect the results of a previous operation and can be used for conditional instruc-
tion execution in a program. The condition codes are extend (X), negative (N), zero
(Z), overflow (V), and carry (C). The user (low-order) byte containing the condition
codes is the only portion of the SR information available at the user privilege level; it
is referenced as the condition code register (CCR) in user programs.
At the supervisor privilege level, software can access the full status register. The upper
byte of this register includes the interrupt priority (IP) mask (three bits), two bits for
placing the processor in one of two tracing modes or disabling tracing, and the super-
visor/user bit for placing the processor at the desired privilege level.
Undefined bits in the status register are reserved by Motorola for future definition. The
undefined bits are read as zeros and should be written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations, but for all CCR operations,
the upper byte is read as all zeros and is ignored when written, regardless of privilege
level.
Refer to
gram of the status register.
31
31
APPENDIX A INTERNAL MEMORY MAP
Figure 3-5 Address Organization in Address Registers
SIGN EXTENDED
Freescale Semiconductor, Inc.
For More Information On This Product,
FULL 32-BIT ADDRESS OPERAND
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
Rev. 25 June 03
1615
16-BIT ADDRESS OPERAND
for bit/field definitions and a dia-
CPU32 ADDR ORG
0
0
MOTOROLA
3-6