MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 394

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.6.1 Power On Reset
10.6.2 Master Reset
10.6.3 System Reset
10.6.4 Register Read and Write Operation
MC68F375
REFERENCE MANUAL
Master Reset
Cycle Start
The device signals a power on reset (IPORB = 0) to the CMFI EEPROM when a full
reset is required. A power on reset is the priority operation for the CMFI EEPROM and
will terminate all other operations, including resetting FRI = 0.
The device signals a master reset (IMSTRSTB = 0) to the CMFI EEPROM when a full
reset is required. A master reset is the 3rd highest priority operation for the CMFI
EEPROM and will terminate all other operations, unless FRI = 1. If FRI = 1 master
reset is blocked to the CMFI EEPROM.
The CMFI EEPROM module uses master reset to initialize all register bits to their
default reset value. If the CMFI EEPROM is in program or erase operation (EHV = 1)
and a master reset is generated, the module will perform the needed interlocks to dis-
able the high voltage without damage to the high voltage circuits. Master reset will
terminate any other mode of operation and force the CMFI EEPROM BIU to a state
ready to receive IMB3 accesses within 4 clocks of the end of master reset.
During master reset the CMFI EEPROM must perform several tasks to assure correct
and reliable operation. In order of execution these tasks are:
The device signals a system reset (ISYSRSTB = 0) to the CMFI EEPROM when
required. A system reset is the 4th highest priority operation and forces the BIU into a
state ready to receive IMB3 accesses and clears the EHV bit, unless FRI = 1. All other
bits shall remain unaltered by a system reset.
The CMFI EEPROM control registers are accessible for read or write operation at all
times while the device is powered up except during master reset, or system reset.
The access time of a CMFI register is at least 2 clocks depending on the state of
WAIT[1:0] for both read and write accesses. Read accesses to reserved registers shall
1. Recover from high voltage operation.
2. Copy the shadow information into the registers.
3. Reset the BIU state machine to receive the first cycle start within 4 clocks of the
final reset clock.
Figure 10-5 Master Reset Configuration Timing
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
512 Clocks (min)
Rev. 25 June 03
4 Clocks
(max)
MOTOROLA
10-24