MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 286

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.8.7.4 Parity Checking
6.8.7.5 Transmitter Operation
MC68F375
REFERENCE MANUAL
mines the position of bit boundaries from transitions within the received waveform, and
adjusts sampling points to the proper positions within the bit period.
Table 6-29
has a maximum system clock rate of 33 MHz).
The PT bit in SCCxR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects
received and transmitted data. The PE bit in SCCxR1 determines whether parity
checking is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data
in a frame (i.e., the bit preceding the stop bit) is used for the parity function. For trans-
mitted data, a parity bit is generated. For received data, the parity bit is checked. When
parity checking is enabled, the PF bit in the SCI status register (SCxSR) is set if a par-
ity error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect
frame size.
The transmitter consists of a serial shifter and a parallel data register (TDRx) located
in the SCI data register (SCxDR). The serial shifter cannot be directly accessed by the
Table 6-30
shows theoretical baud rates for a 40-MHz system clock (the MC68F375
NOTES:
1,250,000.00
Table 6-30 Effect of Parity Checking on Data Size
Baud Rate
1. These rates are based on a 40-MHz system clock.
57,600.00
38,400.00
32,768.00
28,800.00
19,200.00
14,400.00
Nominal
9,600.00
4,800.00
2,400.00
1,200.00
600.00
300.00
Table 6-29 Examples of SCIx Baud Rates
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
M
0
0
1
1
For More Information On This Product,
shows possible data and parity formats.
1,250,000.00
Baud Rate
Go to: www.freescale.com
56,818.18
37,878.79
32,894.74
29,069.77
19,230.77
14,367.81
9,615.38
4,807.69
2,399.23
1,199.62
Actual
600.09
299.98
Rev. 25 June 03
PE
0
1
0
1
8 data bits
7 data bits, 1 parity bit
9 data bits
8 data bits, 1 parity bit
Percent
Error
-1.36
-1.36
-0.22
-0.03
-0.03
-0.01
0.00
0.39
0.94
0.16
0.16
0.16
0.02
Result
Value of
SCxBR
1042
2083
4167
130
260
521
22
33
38
43
65
87
1
1
MOTOROLA
6-52