MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 501

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
0xYF FC08
0xYF FC0A
0xYF FC0C
0xYF FC0E
0xYF FC10 –
0xYF FC12
0xYF FC14
0xYF FC16
0xYF FC18
0xYF FC1A
0xYF FC1C
0xYF FC1E
0xYF FC1F
0xYF FC20
0xYF FC22
0xYF FC24
0xYF FC26
0xYF FC28
0xYF FC2A
0xYF FC2C –
0xYF FC4A
0xYF FC4C –
0xYF FC6A
0xYF FD40 –
0xYF FD7F
0xYF FD80 –
0xYF FDBF
0xYF FDC0 –
0xYF FDDF
Address
Table A-10 QSMCM (Queued Serial Multi-Channel Module) (Continued)
Access
S/U
S/U
S/U
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
SCC1R0
SCC1R1
SC1SR
SC1DR
PORTQS
PQSPAR/
DDRQST
SPCR0
SPCR1
SPCR2
SPCR3
SPSR
SCC2R0
SCC2R1
SC2SR
SC2DR
QSCI1CR
QSCI1SR
SCTQ
SCRQ
REC.RAM
TRAN.RAM
COMD.RAM
Freescale Semiconductor, Inc.
For More Information On This Product,
Symbol
—
INTERNAL MEMORY MAP
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SCI1Control Register 0.
See
SCI1Control Register 1.
See
SCI1 Status Register.
See
SCI1 Data Register.
See
Reserved
QSMCM Port QS Data Register.
See
for bit descriptions.
QSMCM Port QS PIn Assignment Register/
QSMCM Port QS Data Direction Register.
See
tions.
QSPI Control Register 0.
See
QSPI Control Register 1.
See
QSPI Control Register 2.
See
QSPI Control Register 3.
See
QSPI Status Register 3.
See
SCI2 Control Register 0.
See
SCI2 Control Register 1.
See
SCI2 Status Register.
See
SCI2 Data Register.
See
QSCI1 Control Register.
See
QSCI1 Status Register.
See
Transmit Queue Locations.
See
scriptions.
Receive Queue Locations.
See
tions.
Receive Data RAM
See
Transmit Data RAM
See
Command RAM
See
Rev. 25 June 03
Table 6-23
Table 6-24
Table 6-25
Table 6-26
6.6.1 Port QS Data Register (PORTQS)
Table 6-10
Table 6-13
Table 6-15
Table 6-16
Table 6-17
Table 6-18
Table 6-23
Table 6-24
Table 6-24
Table 6-26
Table 6-31
Table 6-32
6.8.7.5 Transmitter Operation
6.8.7.6 Receiver Operation
6.7.2.1 Receive RAM
6.7.2.2 Transmit RAM
Table 6-19
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
and
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Register
Table 6-11
for bit descriptions.
for bit descriptions.
for bit descrip-
for bit descrip-
for bit de-
Size
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
—
8
MOTOROLA
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A-13