MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 399

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
State
S1
S2
S3
The Block protect information and pulse width tim-
Normal read operation still occurs.
The array will accept programming writes
Accesses to the registers are normal register ac-
cesses.
A write to CMFICTL2 cannot change EHV at this
time.
If the write is to a register no data will be stored in
the program page buffers and the CMFI shall re-
main in state S2.
Expanded Program Hardware Interlock Operation:
Program margin reads will occur.
Programming writes are accepted so that all pro-
gram pages may be programmed.
These writes may be to any CMFI array location.
The program page buffers will be updated using
only the data, the lower address (IADDR[5:2]) and
the block address.
Accesses to the registers are normal register ac-
cesses.
A write to CMFICTL2 can change EHV.
If the write is to a register no data will be stored in
the program page buffer.
Normal array reads and register accesses.
First Program Hardware Interlock Write:
ing control can be
Table 10-13 Program Interlock State Descriptions
Normal Operation:
Freescale Semiconductor, Inc.
Mode
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
modified.
Go to: www.freescale.com
Rev. 25 June 03
State
Next
S2
S1
S3
S1
S4
T2
T1
T3
T6
T4
Hardware Interlock
Write to any CMFI array location
This programming write will latch the
selected word of data into the pro-
gramming page buffer and the address
shall be latched to select the location
that will be programmed.
Once a bit has been written then it shall
remain in the program buffer until an-
other write to the word or a write of
SES = 0 or a program margin read de-
termines that the state of the bit needs
no further modification by the program
operation
If the write is to a register no data will
be stored in the program page buffers
and the CMFI shall remain in state S2
Transition Requirement
Write SES = 0 or master reset
Write SES = 0 or master reset
Write PE = 0, SES = 1
Write EHV = 1.
MOTOROLA
10-29