MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 61

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

3.2.4.2 Alternate Function Code Registers
3.2.5 Vector Base Register (VBR)
3.3 Memory Organization
MC68F375
REFERENCE MANUAL
Alternate function code registers (SFC and DFC) contain 3-bit function codes. Func-
tion codes can be considered extensions of the 24-bit linear address that optionally
provide as many as eight 16-Mbyte address spaces. The processor automatically gen-
erates function codes to select address spaces for data and programs at the user and
supervisor privilege levels and to select a CPU address space used for processor
functions (such as breakpoint and interrupt acknowledge cycles).
Registers SFC and DFC are used by the MOVES instruction to specify explicitly the
function codes of the memory address. The MOVEC instruction is used to transfer val-
ues to and from the alternate function code registers. This is a long-word transfer; the
upper 29 bits are read as zeros and are ignored when written.
The VBR contains the base address of the 1024-byte exception vector table, consist-
ing of 256 exception vectors. Exception vectors contain the memory addresses of
routines that begin execution at the completion of exception processing. More
information on the VBR and exception processing can be found in
Processing.
Memory is organized on a byte-addressable basis in which lower addresses corre-
spond to higher order bytes. For example, the address N of a long-word data item
corresponds to the address of the most significant byte of the highest order word. The
address of the most significant byte of the low-order word is N + 2, and the address of
the least significant byte of the long word is N + 3. The CPU32 requires long-word and
word data and all instructions to be aligned on word boundaries. Refer to
If this does not happen, an exception will occur when the CPU32 accesses the
misaligned instruction or data. Data misalignment is not supported.
Freescale Semiconductor, Inc.
For More Information On This Product,
CENTRAL PROCESSOR UNIT
Go to: www.freescale.com
Rev. 25 June 03
3.9 Exception
Figure
MOTOROLA
3-6.
3-7