MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 477

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.8.4.1 BIUMCR — BIUSM Module Configuration Register
BIUMCR — BIUSM Module Configuration Register
MC68F375
REFERENCE MANUAL
STOP
MSB
Bit(s)
12:11
15
0
15
14
13
RESET:
The BIUMCR register contains nine defined bits that allow the software to control five
functions of the CTM: enabling/disabling of the module, response to FREEZE, vector
base address, interrupt arbitration number and access to the time base buses (via the
time base register).
FRZ
14
0
VECT[7:8]
0xYF F200
0xYF F202
0xYF F204
Name
STOP
FRZ
Address
—
13
0
0
VECT7 VECT6
Stop enable. The STOP bit, while asserted, activates the FREEZE signal on the SMB regardless
of the state of the FREEZE signal on the IMB. This completely stops the operation of the CTM.
Note that some submodules may validate this signal with internal enable bits. The BIUSM con-
tinues to operate to allow the CPU access to the submodule’s registers. The SMB FREEZE
signal remains active until reset or until the STOP bit is negated by the CPU (via the IMB).
0 = Allows operation of the CTM.
1 = Stops operation of the CTM.
Freeze enable. The FRZ bit, while asserted, activates the FREEZE signal on the SMB when the
FREEZE signal on the IMB is active. This completely stops the operation of the CTM. Note that
some submodules may validate this signal with internal enable bits. The BIUSM continues to
operate to allow the CPU access to the submodule’s registers. The SMB FREEZE signal
remains active until the FRZ bit is cleared or the IMB FREEZE signal is negated.
0 = Ignores the FREEZE signal on the IMB.
1 = Halts the CTM sub module when the FREEZE signal appears on the IMB.
Reserved
Interrupt vector base number. The interrupt vector base number bits select the interrupt vector
base number for the CTM. Of the 8 bits necessary for vector number definition, the six least sig-
nificant bits are programmed by hardware on a submodule basis, while the two remaining bits
are provided by VECT7 and VECT6.
00 = Vector base number 0x00.
01 = Vector base number 0x40.
10 = Vector base number 0x80.
11 = Vector base number 0xC0.
12
1
15
Freescale Semiconductor, Inc.
11
1
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Table 13-19 BIUMCR Bit Settings
Table 13-18 BIUSM Register Map
IARB2
10
0
Go to: www.freescale.com
BIUSM module configuration register (BIUMCR)
IARB1
9
0
Rev. 25 June 03
BIUSM time base register (BIUTBR)
IARB0
BIUSM test register (BIUTST)
8
0
.
7
0
0
8 7
Description
6
0
0
TBRS1
5
0
4
0
0
3
0
0
2
0
0
0xYF F200
MOTOROLA
0
1
0
0
TBRS0
13-51
LSB
0
0