MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 224

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

CCW — Conversion Command Word Table
RESET:
MC68F375
REFERENCE MANUAL
MSB
15
0
• Software can change the queue operating mode to disabled mode. Any conver-
• Software can change the queue operating mode to another valid mode. Any con-
• For low power operation, software can set the stop mode bit to prepare the mod-
• When the freeze enable bit is set by software and the IMB internal FREEZE line
cuted when queue 2 was suspended. Alternately, conversions can restart with the
aborted queue 2 CCW entry. The RESUME bit in QACR2 allows the software to
select where queue 2 begins after suspension. By choosing to re-execute all of
the suspended queue 2 queue and subqueue CCWs, all of the samples are guar-
anteed to have been taken during the same scan pass. However, a high trigger
event rate for queue 1 can prohibit the completion of queue 2. If this occurs, the
software may choose to begin execution of queue 2 with the aborted CCW entry.
sion in progress for that queue is aborted. Putting a queue into the disabled mode
does not power down the converter.
version in progress for that queue is aborted. The queue restarts at the beginning
of the queue, once an appropriate trigger event occurs.
ule for a loss of clocks. The QADC64 aborts any conversion in progress when the
stop mode is entered.
is asserted, the QADC64 freezes at the end of the conversion in progress. When
internal FREEZE is negated, the QADC64 resumes queue execution beginning
with the next CCW entry.
14
0
RESERVED
13
0
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
12
0
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
10
0
Go to: www.freescale.com
P
U
9
Rev. 25 June 03
BYP
U
8
U
7
IST
U
6
U
5
0xYF F600 – 0xYF F67F
U
4
U
3
CHAN
U
2
MOTOROLA
U
1
5-48
LSB
U
0