MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 183

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

5.5.2 Freeze Mode
5.5.3 Supervisor/Unrestricted Address Space
MC68F375
REFERENCE MANUAL
power stop mode, the QADC64 requires some recovery time (t
APPENDIX E ELECTRICAL
after the STOP bit is cleared.
In low-power stop mode, the BIU state machine and logic do not shut down: the
QADC64MCR and the interrupt register (QADC64INT) are fully accessible and are not
reset. The data direction register (DDRQA), port data register (PORTQA/PORTQB),
and control register 0 (QACR0) are not reset and are read-only accessible. The RAM
is not reset and is not accessible. Control register 1 (QACR1), control register 2
(QACR2), and the status registers (QASR0 and QASR1) are reset and are read-only
accessible. In addition, the periodic/interval timer is held in reset during stop mode.
If the STOP bit is clear, low-power stop mode is disabled. The STOP bit must be clear
to program CCW’s into RAM or read results from RAM.
The QADC64 enters freeze mode when background debug mode is enabled and a
breakpoint is processed. This is indicated by assertion of the FREEZE line on the
IMB3. The FRZ bit in QADC64MCR determines whether or not the QADC64 responds
to an IMB FREEZE assertion. Freeze mode is useful when debugging an application.
When the IMB FREEZE line is asserted and the FRZ bit is set, the QADC64 finishes
any conversion in progress and then freezes. Depending on when the FREEZE is
asserted, there are three possible queue freeze scenarios:
When the QADC64 enters the freeze mode while a queue is active, the current CCW
location of the queue pointer is saved.
During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer
is held in reset. External trigger events that occur during the freeze mode are not cap-
tured. The BIU remains active to allow IMB access to all QADC64 registers and RAM.
Although the QADC64 saves a pointer to the next CCW in the current queue, the soft-
ware can force the QADC64 to execute a different CCW by writing new queue
operating modes for normal operation. The QADC64 looks at the queue operating
modes, the current queue pointer, and any pending trigger events to decide which
CCW to execute.
If the FRZ bit is clear, assertion of the IMB FREEZE line is ignored.
The QADC64 memory map is divided into two segments: supervisor-only data space
and assignable data space. Access to supervisor-only data space is permitted only
• When a queue is not executing, the QADC64 freezes immediately.
• When a queue is executing, the QADC64 completes the current conversion and
• If during the execution of the current conversion, the queue operating mode for
then freezes.
the active queue is changed, or a queue 2 abort occurs, the QADC64 freezes im-
mediately.
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
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CHARACTERISTICS) to stabilize the analog circuits
Rev. 25 June 03
SR
, see
Table E-12
MOTOROLA
5-7
in