MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 605

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

interrupt acknowledge - see IACK
interrupt arbitration number 13-52
Interrupt Level of SCI (ILSCI) 6-8
Interrupts
interrupts
Inter-transfer delay 6-14
Invalid channel number 5-49
IP 6-6, 8-5
IPIPE 4-66, 4-67
IPT 7-9
IRQ 8-5
IRQ7 4-70, 4-71
IST 5-28, 5-49
LBUF 7-28
Least significant bit (LSB) 5-14
Length of delay after transfer (DTL) 6-18
Limp status (SLIMP) 4-23
LJSRR 5-51
loading the MCSM counter register 13-10
LOC 4-56
Lock
Loop
LOOPQ 6-20
LOOPS 6-46
LOSCD 4-22, 4-23
Loss
Loss of clock reset (LOC) 4-56
Low power stop (LPSTOP)
Lowest buffer transmitted first (LBUF) 7-28
Low-power
MC68F375
REFERENCE MANUAL
priority
processing summary 4-73
vector
QADC 5-29
SCIM2 4-70
TOUCAN 7-19
TPU 8-5
DASM 13-34
FCSM 13-6
MCSM 13-11
PWMSM 13-42
SASM 13-17, 13-18, 13-19
setting the priority level 13-52
spurious interrupt vector 13-52
vector base number 13-51
/release/busy mechanism 7-15
mode 3-15
of reference signal 4-22
-of-clock oscillator (LOSCD) 4-23
CPU32 3-15
QADC 5-6
QSM 6-5
broadcast cycle 4-46
and recognition 4-70
mask (IP) field 3-6, 4-70, 6-6, 8-5
number 6-6
(LOOPS) 6-46
instruction sequence 3-16
–L–
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
INDEX
LPSTOP 3-15, 4-21, 4-30
LR 8-18
LSB 3-4, 5-14
M 6-46, 6-51
M6800 bus E clock signal 4-65
M68000 family
Mask
Master
maximum external clock frequency
MC68010 3-15
MC68020 3-10, 3-15
MCPWM D-21
MCSM
MCSMCNT 13-14
CPU space cycle 4-46
interrupt mask level 4-46
operation 4-20
stop mode enable (STOP)
flowchart 4-22
compatibility 3-15
development support 3-19
examples for normal/extended messages 7-8
registers (RX) 7-7
/slave mode select (MSTR) 6-17
FCSM 13-6, 13-8
MCSM 13-11, 13-13
as free-running counter 13-11
block diagram 13-9
clock input pin - CTMC 13-11, 13-13
clocks 13-11
counter 13-10
counter overflow 13-13
counter register 13-14
driving the time base bus 13-13
effect of reset 13-10
event counter 13-11
flag clearing 13-13
freeze 13-12
input pin - CTML 13-11
interrupts 13-11
loading the counter register 13-10
maximum external clock frequency 13-11, 13-13
MCSMCNT — MCSM counter register 13-14
MCSMML — MCSM modulus latch register 13-14
MCSMSIC — MCSM status/interrupt/control register
modulus latch 13-10
modulus latch register 13-14
modulus load input pin - CTML 13-13
reserved registers 13-12
selecting CTML edge sensitivity 13-13
selecting the clock source 13-13
selecting the time base bus 13-11
setting the interrupt level 13-13
status/interrupt register 13-12
QADC 5-35
SCIM2 4-30
TPU 8-11
13-12
–M–
MOTOROLA
Index-7