MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 175

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.10.4.4 Port F Edge-Detect Flag Register
PORTFE — Port F Edge-Detect Flag Register
4.10.4.5 Port F Edge-Detect Interrupt Vector
PFIVR — Port F Edge-Detect Interrupt Vector Register
4.10.4.6 Port F Edge-Detect Interrupt Level
PFLVR — Port F Edge-Detect Interrupt Level Register
4.10.5 Port G
MC68F375
REFERENCE MANUAL
RESET:
RESET:
RESET:
When the corresponding pin is configured for edge detection, a PORTFE bit is set if
an edge is detected. PORTFE bits remain set, regardless of the subsequent state of
the corresponding pin, until cleared. To clear a bit, first read PORTFE, then write the
bit to zero. When a pin is configured for general-purpose I/O or for use as an interrupt
request input, PORTFE bits do not change state. Bits [15:8] are reserved and will
always read zero.
This register determines which vector in the exception vector table is used for inter-
rupts generated by the port F edge-detect logic. Program PFIVR[7:0] to the value
pointing to the appropriate interrupt vector. Bits [15:8] are reserved and will always
read zero.
This register determines the priority level of the port F edge-detect interrupt. The reset
value is 0x00, indicating that the interrupt is disabled. When several sources of inter-
rupts from the SCIM are arbitrating for the same level, the port F edge-detect interrupt
has the lowest arbitration priority. Bits [15:8] are reserved and will always read zero.
Port G is available in single-chip mode only. These pins are always configured for use
as general-purpose I/O in single-chip mode.
PEF7
MSB
MSB
MSB
7
0
7
0
7
0
0
PEF6
6
0
6
0
6
0
0
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
PEF5
5
0
5
0
5
0
0
Go to: www.freescale.com
PEF4
Rev. 25 June 03
4
0
4
0
4
0
0
PFIVR[7:0]
PEF3
3
0
3
0
3
0
0
PEF2
2
0
2
0
2
0
PFLV[2:0]
PEF1
1
0
1
0
1
0
0xYF FA2B
0xYF FA2D
0xYF FA29
MOTOROLA
PEF0
LSB
LSB
LSB
0
0
0
0
0
0
4-93