MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 411

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

RAMBAH1, RAMBA1L — SRAM Base Address Registers
RAMBAH2, RAMBAL2
RAMBAH3, RAMBAL3
RAMBAH4, RAMBAL4
RAMBAH, RAM1BAL
11.4 Operation
MC68F375
REFERENCE MANUAL
MSB
MSB
Bit(s)
31:16
31
15
15:9
0
0
8:0
RESET:
RESET:
the SRAM array address block. The SRAM array base address is placed on a 512, 1K,
2K or 4-Kbyte block boundary (block size greater than or equal to the size of the array).
RAMBAH and RAMBAL may only be written while the SRAM is in STOP mode STOP
= “1” and the lock bit is not set RLCK = “0”. Once the RLCK bit is set, writes will have
no effect on RAMBAH and RAMBAL. This will prevent runaway software from inad-
vertently re-mapping the array. The SRAM must be in STOP mode while RAMBAH or
RAMBAL are written this prevents inadvertent intermediate array mapping to be
acknowledged.
The SRAM module has several modes of operation. The following sections describe
SRAM module operation in each of these modes.
30
14
0
0
RAMBAH
RAMBAL
Name
—
29
13
0
0
RAMBAL
Array base address high. With STOP asserted the base Address field of RAMBAH may be
changed so that the array may be placed at the desired address in the memory map. This must
be done by a supervisor program since the register is in supervisor data space. To lock the base
address field, RLCK in the RAMMCR should be set. This will prevent the base address field from
being changed until the next master reset.
Array base address low. With STOP asserted the base Address field of RAMBAL may be
changed so that the array may be placed at the desired address in the memory map. This must
be done by a supervisor program since the register is in supervisor data space. To lock the base
address field, RLCK RAMMCR should be set. This will prevent the base address field from being
changed until the next master reset.
Reserved
28
12
0
0
Table 11-3 RAMBAH, RAMBAL Bit Settings
Freescale Semiconductor, Inc.
27
11
STATIC RANDOM ACCESS MEMORY (SRAM)
0
0
For More Information On This Product,
26
10
0
0
Go to: www.freescale.com
25
0
9
0
Rev. 25 June 03
24
0
8
0
RAMBAH
23
0
7
0
Description
22
0
6
0
21
0
5
0
RESERVED
0xYF FB04, 0xYF FB06
0xYF F84C, 0xYF F84E
0xYF F85C, 0xYF F85E
0xYF F844, 0xYF F846
0xYF F854, 0xYF F856
20
0
4
0
19
0
3
0
18
0
2
0
MOTOROLA
17
0
1
0
LSB
LSB
11-5
16
0
0
0