MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 36

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
• Time processing unit (TPU3):
• 6-Kbyte TPU emulation RAM (DPTRAM).
• 256K Byte 1T Flash EEPROM (CMFI).
• SRAM
• Late programmable read only memory – ROM:
• CAN2.0B controller module (TouCAN ):
• Configurable timer module 9 (CTM9):
— Dual function I/O port pins.
— 16 channels – each is associated with a pin.
— Each channel can perform any time function.
— Each time function may be assigned to more than one channel.
— Each channel has an event register comprised of: 16-bit capture register, 16-
— Each channel can be programmed to perform match or capture operations
— TCR1 is clocked from the internal TPU3 system clock.
— TCR2 may be clocked or gated from the external T2CLK pin.
— All time primitives are microcoded.
— 4 Kbytes of microstore program ROM space.
— All channels have eight 16-bit parameter registers.
— A hardware scheduler with three priority levels is included.
— Resolution is one system clock period.
— Modulus prescaler (DIV 2, 4, 6...... 62, 64)
— Can be used as system RAM or TPU microcode storage.
—
—
— External V
— 8-Kbyte static RAM (SRAM):
— 4 x 512-byte static RAM (SRAM):
— 512-byte modules can overlay any 512-byte portion (on 512-byte boundaries)
— 8-Kbyte array, accessible as bytes or words.
— User selectable default base address.
— User selectable bootstrap ROM function.
— Full implementation of CAN protocol specification – Version 2.0B.
— Standard/extended data and remote frames (up to 109/127 bits long).
— Programmable bit rate up to 1 Mbit/sec, derived from system clock.
— 16 Rx/Tx message buffers of 0-8 bytes data length, of which 2 buffers are con-
— Programmable global Rx masks.
— Programmable transmit-first scheme: lowest ID or lowest buffer number.
— Low power “SLEEP” mode, with programmable “WAKE UP” on bus activity.
— Automatic time-stamping of received and transmitted messages.
— 1 bus interface unit submodule (BIUSM).
— 1 counter prescaler submodule (CPSM).
— 1 free-running counter submodule (FCSM).
bit compare/match register, 16-bit greater-than-or-equal-to comparator.
with one or both of the two 16-bit free running timer count registers (TCR1 and
TCR2).
of the CMFI module.
figurable to work as Rx buffers with specific programmable masks.
5 V program/erase.
Block 0 protected by an external pin.
STBY
Freescale Semiconductor, Inc.
For More Information On This Product,
pin for separate standby supply.
OVERVIEW DESCRIPTION
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
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