MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 227

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

RJURR — Right Justified, Unsigned Result Register
LJSRR — Left Justified, Signed Result Register
LJURR — Left Justified, Unsigned Result Register
5.12.11 Result Word Table
RESET:
RESET:
RESET:
MC68F375
REFERENCE MANUAL
NOTES:
MSB
MSB
MSB
15
15
S
15
0
1. S = Sign bit.
1
The result word table is a 64-word long, 10-bit wide RAM. The QADC64 writes a result
word after completing an analog conversion specified by the corresponding CCW. The
result word table can be read or written, but in normal operation, software reads the
result word table to obtain analog conversions from the QADC64. Unimplemented bits
are read as zeros, and write operations have no effect.
While there is only one result word table, the data can be accessed in three different
alignment formats:
The left justified, signed format corresponds to a half-scale, offset binary, two’s com-
plement data format. The data is routed onto the IMB according to the selected format.
The address used to access the table determines the data alignment format. All write
operations to the result word table are right justified.
The conversion result is unsigned, right justified data. Unused bits return zero when
read.
The conversion result is signed, left justified data. Unused bits return zero when read.
• Right justified, with zeros in the higher order unused bits.
• Left justified, with the most significant bit inverted to form a sign bit, and zeros in
• Left justified, with zeros in the unused lower order bits.
the unused lower order bits.
14
14
14
0
RESERVED
13
13
13
0
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
12
12
12
0
Freescale Semiconductor, Inc.
11
11
11
RESULT
0
For More Information On This Product,
RESULT
10
10
10
0
Go to: www.freescale.com
9
9
9
Rev. 25 June 03
8
8
8
7
7
7
6
6
6
5
5
0
5
0
RESULT
0xYF F680 – 0xYF F6FE
0xYF F780 – 0xYF F7FE
0xYF F700 – 0xYF F77E
4
4
0
4
0
RESERVED
RESERVED
3
3
0
3
0
2
2
0
2
0
MOTOROLA
1
1
0
1
0
5-51
LSB
LSB
LSB
0
0
0
0
0