MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 373

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.1.2 Features of the CMFI
MC68F375
REFERENCE MANUAL
access the required information is 2 system clocks. Reads will always begin with a 2
clock access. If the IMB3 indicates a burst access the following access(es) will be 1
clock until the CMFI reaches the end of the burst buffer or the IMB3 terminates the
burst access. During the burst reads, the CMFI increments the address by one word
each access. The end of the burst buffer is indicated by the highest location within the
burst buffer being read, ADDR[4:0] = 0x1F. All burst accesses are aligned to the IMB3
data bus, ignoring the byte address(es). To prevent the BIU from unnecessarily
accessing the array, the CMFI EEPROM shall monitor the IMB3 address to determine
if the required information is in one of the two current burst buffers and the access is
valid for the module. This process is designed to reduce power consumption by the
CMFI.
In normal operation write accesses to the CMFI array are not recognized.
The CMFI EEPROM module requires an external program or erase voltage, V
program or erase the array or any of its control register shadow bits. Special control
logic is included to require a specific series of read and write accesses before program
or erase operation is allowed.
To improve program performance, the CMFI programs up to eight unique 64-byte
pages simultaneously in eight separate array blocks. These 64 bytes are aligned to the
low order addresses, IADDR[5:0], to form a program page buffer. Each of the pages
being programmed simultaneously are located at the same block offset address,
IADDR[23:15|14]. Erase is performed on one or more of the selected array blocks
simultaneously.
• MOTOROLA’s 1 transistor, MoneT, FLASH bit cell.
• -40 to 125 C operating temperature range.
• V
• Shadow and bootstrap information stored in special FLASH NVM locations.
• 256-Kbyte array size.
• Array distributed in 8 blocks.
• Program up to 512 bytes at a time.
• Self-timed program and erase pulses.
— Operational at 2. 7 V.
— Up to 40 MHz operation at V
— Erase by array block(s).
— Common array block size of 32 Kbytes.
— Array lock protection for program and erase
— Array address attributes restriction control.
— Program up to eight 64-byte pages simultaneously.
— Pages located at the same offset address.
— Internal pulse width timing control using system clock frequencies from 8.0
DD
• Built-in margin reads for both program and erase verify reads.
• Array access disabled while programming or erasing.
• Select between supervisor and supervisor/user spaces.
• Select between data and instruction/data spaces.
3. 0 V to 3. 6 V operating range.
Freescale Semiconductor, Inc.
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
DD
= 3. 0 V, 150 C = T
operations.
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MOTOROLA
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