MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 151

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.7.8.6 Emulation Mode Selection
4.7.9 Use of the Three-State Control Pin
MC68F375
REFERENCE MANUAL
Refer to
(CPU32RM/AD)
Reference Manual (SCIMRM/AD)
ISTICS
The SCIM2E contains logic that can be used to replace on-chip ports externally. The
SCIM2E also contains special support logic that allows external emulation of internal
ROM. These emulation support features enable the development of a single-chip
application in expanded mode.
Emulation mode is a special type of 16-bit expanded operation. It is entered by holding
DATA10 low, BERR high, and DATA1 low during reset. In emulation mode, all port A,
B, E, G, and H data and data direction registers and the port E pin assignment register
are mapped externally. The port C data, port F data and data direction registers, and
port F pin assignment register are accessible normally in emulation mode.
The port emulation chip select (CSE) is asserted whenever any of the externally
mapped registers are addressed. The signal is asserted on the falling edge of AS. The
SCIM2E does not respond to these accesses, allowing external logic, such as a port
replacement unit (PRU) to respond. Accesses to externally mapped registers require
three clock cycles.
CMFI and ROM emulation is enabled by holding BERR high and by holding low
DATA1, DATA10, and DATA13 when RESET is released. While CMFI and ROM emu-
lation mode is enabled, the emulation memory chip-select signal (CSM) is asserted
whenever an access to an address assigned to the masked ROM module or CMFI
module is made.
CMFI and ROM modules do not acknowledge IMB accesses while in emulation mode.
This causes the SCIM2E to run an external bus cycle for each access. The bus cycle
is terminated by the module, however, ensuring consistent timing.
Asserting the three-state control (TSC) input to a logic 0 causes the MCU to place all
output drivers in a disabled, high-impedance state. TSC must remain asserted for
approximately ten clock cycles in order for drivers to change state.
When the SCIM2E clock synthesizer is used, PLL ramp-up time affects how long the
ten cycles take. Worst case is approximately 20 ms from TSC assertion.
When an external clock signal is applied, pins go high-impedance as soon after TSC
assertion as approximately ten clock pulses have been applied to the EXTAL pin.
for more information concerning BKPT signal timing.
3.10.2 Background Debug Mode
for more information on background debug mode. Refer to the
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
and
APPENDIX E ELECTRICAL CHARACTER-
and the
CPU32 Reference Manual
MOTOROLA
SCIM
4-69