MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 456

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
The output flip-flop is set when a match occurs on channel A. The output flip-flop is
reset when a match occurs on channel B. The polarity of the output signal is selected
by the EDPOL bit. The output flip-flop level can be obtained at any time by reading the
IN bit.
If subsequent enabled output compares occur on channels A and B, the output pulses
continue to be output, regardless of the state of the FLAG bit.
At any time, the FORCA and FORCB bits allow the software to force the output flip-
flop to the level corresponding to a comparison on channel A or B, respectively. Note
that the FLAG bit is not affected by these ‘force’ operations.
Totem pole or open-drain output circuit configurations can be selected using the WOR
bit in the DASMSIC register.
Single Shot Output Pulse Operation — The single shot output pulse operation is
selected by writing the leading edge value of the desired pulse to data register A and
the trailing edge value to data register B. A single pulse will be output at the desired
time, thereby disabling the comparators until new values are written to the data regis-
ters. In this mode, registers A and B2 are accessible to the user software (at
consecutive addresses).
used to generate a single output pulse.
There is no hardware protection to disable comparator B while com-
parator A is enabled. It is the user’s responsibility to load data
registers A and B with the values needed to produce the desired out-
put pulse.
If both channels are loaded with the same value they will try to force
different levels on the output flip-flop. Hardware protection circuitry
ensures that no contention occurs and the output flip-flop provides a
logic zero level output.
Freescale Semiconductor, Inc.
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Figure 13-10
Go to: www.freescale.com
Rev. 25 June 03
WARNING
provides an example of how the DASM can be
NOTE
MOTOROLA
13-30