MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 413

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

11.4.4 STOP Operation
11.4.5 Overlay Operation
MC68F375
REFERENCE MANUAL
Note that a long word write will be completed coherently only if the reset occurs during
the second write bus cycle. If reset occurs during the first write bus cycle, only the first
word will be written to the SRAM array and the second write will not be allowed to
occur. In this case, the long word data contained in the SRAM will not be coherent. The
first word will contain the most significant half of the new long word information and the
second word will contain the least significant half of the old long word information.
If a reset is generated by an asynchronous reset such as the loss of clocks or software
watchdog time-out, the contents of the standby SRAM array are not guaranteed.
The assertion of the STOP control bit of the RAMMCR (see
ration Register
consuming state. The register block may still be accessed to allow the STOP control
bit to be cleared and the array base address registers to be updated, see
Base Address Registers (RAMBAH,
When in stop mode, the SRAM array can not be read or written. All data in the array
will be retained. Switching to V
ified value when the SRAM module is in stop mode.
The four 512-byte SRAM blocks can be used independently of the main 8K SRAM
array. The blocks can be initialized to be continuous with the main array or can be used
to overlay the flash module. The overlay feature is enabled whenever an overlay
SRAM module base address is mapped over the flash array address space. The 512-
byte SRAM block should be placed on a 512-byte boundary and will respond to any
access to the overlayed section of the flash and will disable the flash contents from
being read.
(RAMMCR)) causes the SRAM module to enter its lowest power
Freescale Semiconductor, Inc.
STATIC RANDOM ACCESS MEMORY (SRAM)
For More Information On This Product,
Go to: www.freescale.com
STBY
Rev. 25 June 03
will occur as normal if V
RAMBAL).
DDL
11.3.1 Module Configu-
drops below its spec-
11.3.2 Array
MOTOROLA
11-7