MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 130

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.5.1 Bus Errors
4.6.5.2 Double Bus Faults
MC68F375
REFERENCE MANUAL
The CPU32 treats bus errors as a type of exception. Bus error exception processing
begins when the CPU32 detects assertion of the IMB BERR signal (by the internal bus
monitor or an external source) while the HALT signal remains negated.
BERR assertions do not force immediate exception processing. The signal is synchro-
nized with normal bus cycles and is latched into the CPU32 at the end of the bus cycle
in which it was asserted. Because bus cycles can overlap instruction boundaries, bus
error exception processing may not occur at the end of the instruction in which the bus
cycle begins. Timing of BERR detection/acknowledge is dependent upon several
factors:
Because of these factors, it is impossible to predict precisely how long after occur-
rence of a bus error the bus error exception is processed.
Exception processing for bus error exceptions follows the standard exception process-
ing sequence. Refer to
special case of bus error, called double bus fault, can abort exception processing.
BERR assertion is not detected until an instruction is complete. The BERR latch is
cleared by the first instruction of the BERR exception handler. Double bus fault occurs
in three ways:
• Which bus cycle of an instruction is terminated by assertion of BERR.
• The number of bus cycles in the instruction during which BERR is asserted.
• The number of bus cycles in the instruction following the instruction in which
• Whether BERR is asserted during a program space access or a data space ac-
1. When bus error exception processing begins and a second BERR is detected
2. When one or more bus errors occur before the first instruction after a reset ex-
3. A bus error occurs while the CPU32 is loading information from a bus error
BERR is asserted.
cess.
before the first instruction of the exception handler is executed.
ception is executed.
If DSACK or BERR remain asserted into S2 of the next bus cycle,
that cycle may be terminated prematurely.
The external bus interface does not latch data when an external bus
cycle is terminated by a bus error. When this occurs during an
instruction prefetch, the IMB precharge state (bus pulled high, or
0xFFFF) is latched into the CPU32 instruction register, with indeter-
minate results.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
3.9 Exception Processing
Go to: www.freescale.com
Rev. 25 June 03
WARNING
CAUTION
for more information. However, a
MOTOROLA
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