MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 249

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.7.1 QSPI Registers
MC68F375
REFERENCE MANUAL
A dedicated 160-byte RAM is used to store received data, data to be transmitted, and
a queue of commands. The CPU can access these locations directly. This allows serial
peripherals to be treated like memory-mapped parallel devices.
The command queue allows the QSPI to perform up to 32 serial transfers without CPU
intervention. Each queue entry contains all the information needed by the QSPI to
independently complete one serial transfer.
A pointer identifies the queue location containing the data and command for the next
serial transfer. Normally, the pointer address is incremented after each serial transfer,
but the CPU can change the pointer value at any time. Support for multiple-tasks can
be provided by segmenting the queue.
The QSPI has four peripheral chip-select pins. The chip-select signals simplify inter-
facing by reducing CPU intervention. If the chip-select signals are externally decoded,
16 independent select signals can be generated.
Wrap-around mode allows continuous execution of queued commands. In wrap-
around mode, newly received data replaces previously received data in the receive
RAM. Wrap-around mode can simplify the interface with A/D converters by continu-
ously updating conversion values stored in the RAM.
Continuous transfer mode allows transfer of an uninterrupted bit stream. From 8 to 512
bits can be transferred without CPU intervention. Longer transfers are possible, but
minimal intervention is required to prevent loss of data. A standard delay of 17 system
clocks (0.8 µs with a 40-MHz system clock) is inserted between the transfer of each
queue entry.
The QSPI memory map, shown in
control registers, four QSPI control registers (SPCR[0:3]), the status register (SPSR),
and the QSPI RAM. Registers and RAM can be read and written by the CPU. The
memory map can be divided into supervisor-only data space and assignable data
space. The address offsets shown are from the base address of the QSMCM module.
Refer to
Figure 1-2
Freescale Semiconductor, Inc.
for a diagram of the MC68F375 internal memory map.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Table
6-12, includes the QSMCM global and pin
MOTOROLA
6-15