MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 357

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

8.4.10 Channel Priority Registers
CPR0 — Channel Priority Register 0
CPR1 — Channel Priority Register 1
MC68F375
REFERENCE MANUAL
MSB
MSB
15
15
CH[15:0]
CH[15:0]
0
0
RESET:
RESET:
Name
Name
The channel priority registers (CPR1, CPR2) assign one of three priority levels to a
channel or disable the channel.
CH 15
CH 7
14
14
0
0
Encoded type of host service. The host service request field selects the type of host service request for
the time function selected on a given channel. The meaning of the host service request bits depends
on the time function specified.
A host service request field cleared to 0b00 signals the host that service is completed by the
microengine on that channel. The host can request service on a channel by writing the corresponding
host service request field to one of three non-zero states. The CPU must monitor the host service
request register until the TPU3 clears the service request to 0b00 before any parameters are changed
or a new service request is issued to the channel.
Encoded channel priority levels.
channel priority encoding.
13
13
0
0
CH 14
CH 6
12
12
0
0
Freescale Semiconductor, Inc.
11
11
0
0
CHx[1:0]
For More Information On This Product,
CH 13
CH 5
00
01
10
11
Table 8-13 HSSRx Bit Settings
Table 8-14 CPRx Bit Settings
Table 8-15 Channel Priorities
10
10
0
0
TIME PROCESSOR UNIT 3
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Disabled
Service
9
0
9
0
Table 8-15
Middle
CH 12
High
Low
CH 4
Rev. 25 June 03
8
0
8
0
indicates the number of time slots guaranteed for each
Description
Description
Guaranteed Time Slots
7
0
7
0
CH 11
CH 3
2 out of 7
4 out of 7
1 out of 7
6
0
6
0
—
5
0
5
0
CH 10
CH 2
4
0
4
0
3
0
3
0
CH 9
CH 1
2
0
2
0
0xYF FE1C
0xYF FE1E
MOTOROLA
1
0
1
0
CH 8
CH 0
LSB
LSB
8-17
0
0
0
0