MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 241

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

QSMCMMCR — QSMCM Configuration Register
6.5.6 QSMCM Test Register (QTEST)
6.5.7 QSMCM Interrupt Level Registers (QILR, QIVR, QSPI_IL)
QILR — QSM Interrupt Levels Register
MC68F375
REFERENCE MANUAL
RESET:
STOP
MSB
Bit(s)
15
0
13:8
The QTEST register is used for factory testing of the MCU.
The values of ILQSPI[2:0] and ILSCI[2:0] in QILR and QSPI_IL determine the priority
of QSPI and SCI interrupt requests.
QIVR determines the value of the interrupt vector number the QSMCM supplies when
it responds to an interrupt acknowledge cycle. At reset, QIVR is initialized to 0x0F, the
uninitialized interrupt vector number. To use interrupt-driven serial communication, a
user-defined vector number must be written to QIVR.
6:4
3:0
15
14
7
7
0
FRZ1
RESET:
14
0
Name
STOP
SUPV
FRZ1
IARB
13
0
—
—
6
0
12
0
Stop enable. Refer to
0 = Normal clock operation
1 = Internal clocks stopped
Freeze1 bit. Refer to
0 = Ignore the FREEZE signal
1 = Halt the QSMCM (on transfer boundary)
Reserved
Supervisor /Unrestricted. Refer to
0 = Assigned registers are unrestricted (user access allowed)
1 = Assigned registers are restricted (only supervisor access allowed)
Reserved
Interrupt arbitration number. IARB determines QSMCM interrupt arbitration priority. An
IARB field can be assigned a value from 0b0001 (lowest priority) to 0b1111 (highest
value). Note that the logic associated with the IARB field is implemented for bus masters
with interrupt acknowledge cycles (IACK).
Freescale Semiconductor, Inc.
RESERVED
QUEUED SERIAL MULTI-CHANNEL MODULE
RESERVED
11
For More Information On This Product,
0
Table 6-3 QSMCMMCR Bit Settings
5
0
10
0
Go to: www.freescale.com
9
0
Rev. 25 June 03
6.5.2 Freeze
4
0
6.5.1 Low-Power Stop
8
0
SUPV
7
1
6.5.3 Access
Operation.
3
0
Description
6
0
RESERVED
Operation.
5
0
Protection.
2
0
4
0
ILSCI[2:0]
3
0
1
0
2
0
0xYF FC00
0xYF FC04
IARB
MOTOROLA
1
0
0
0
LSB
0
0
6-7