MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 323

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

7.6.2 Low-Power Stop Mode
MC68F375
REFERENCE MANUAL
bus off state. Once one of these conditions exists, the TouCAN waits for the comple-
tion of all internal activity. Once this happens, the following events occur:
After engaging one of the mechanisms to place the TouCAN in debug mode, the user
must wait for the FRZACK bit to be set before accessing any other registers in the Tou-
CAN; otherwise unpredictable operation may occur.
To exit debug mode, the IMB FREEZE line must be negated or the HALT bit in
CANMCR must be cleared.
Once debug mode is exited, the TouCAN resynchronizes with the CAN bus by waiting
for 11 consecutive recessive bits before beginning to participate in CAN bus
communication.
Before entering low-power stop mode, the TouCAN waits for the CAN bus to be in an
idle state, or for the third bit of intermission to be recessive. The TouCAN then waits
for the completion of all internal activity (except in the CAN bus interface) to be com-
plete. Then the following events occur:
To exit low-power stop mode:
When the TouCAN is in low-power stop mode, a recessive to dominant transition on
the CAN bus causes the WAKEINT bit in the error and status register (ESTAT) to be
set. This event generates an interrupt if the WAKEMSK bit in CANMCR is set.
Consider the following notes regarding low-power stop mode:
• The TouCAN stops transmitting or receiving frames.
• The prescaler is disabled, thus halting all CAN bus communication.
• The TouCAN ignores its RX pins and drives its TX pins as recessive. The Tou-
• The CPU is allowed to read and write the error counter registers.
• The TouCAN shuts down its clocks, stopping most internal circuits, thus achieving
• The bus interface unit continues to operate, allowing the CPU to access the mod-
• The TouCAN ignores its RX pins and drives its TX pins as recessive.
• The TouCAN loses synchronization with the CAN bus, and the STOPACK and
• Reset the TouCAN either by asserting one of the IMB3 reset lines or by asserting
• Clear the STOP bit in CANMCR.
• The TouCAN module can optionally exit low-power stop mode via the self-wake
CAN loses synchronization with the CAN bus and the NOTRDY and FRZACK bits
in CANMCR are set.
maximum power savings.
ule configuration register.
NOTRDY bits in the module configuration register are set.
the SOFTRST bit CANMCR.
mechanism. If the SELFWAKE bit in CANMCR was set at the time the TouCAN
entered stop mode, then upon detection of a recessive to dominant transition on
the CAN bus, the TouCAN clears the STOP bit in CANMCR and its clocks begin
running.
Freescale Semiconductor, Inc.
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
7-17