MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 331

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

CANICR — TouCAN Interrupt Configuration Register
7.8.2 TouCAN Interrupt Configuration Register
MC68F375
REFERENCE MANUAL
MSB
15
Bit(s)
0
RESET:
3:0
6
5
4
14
0
SELFWAKE
STOPACK
RESERVED
IARB[3:0]
Name
APS
13
0
If the TouCAN issues an interrupt request after reset and before
IVBA[2:0] is initialized, it will drive 0x0F as the “uninitialized” interrupt
vector in response to a CPU32 interrupt acknowledge cycle, regard-
less of the specific event.
12
0
Table 7-11 TCNMCR Bit Settings (Continued)
Self wake enable. This bit allows the TouCAN to wake up when bus activity is detected after
the STOP bit is set. If this bit is set when the TouCAN enters low-power stop mode, the Tou-
CAN will monitor the bus for a recessive to dominant transition. If a recessive to dominant
transition is detected, the TouCAN immediately clears the STOP bit and restarts its clocks.
If a write to CANMCR with SELFWAKE set occurs at the same time a recessive-to-dominant
edge appears on the CAN bus, the bit will not be set, and the module clocks will not stop.
The user should verify that this bit has been set by reading CANMCR. Refer to
Power Stop Mode
0 = Self wake disabled.
1 = Self wake enabled.
Auto power save. The APS bit allows the TouCAN to automatically shut off its clocks to save
power when it has no process to execute, and to automatically restart these clocks when it
has a task to execute without any CPU intervention.
0 = Auto power save mode disabled; clocks run normally.
1 = Auto power save mode enabled; clocks stop and restart as needed.
its clocks, it sets the STOPACK bit. This bit should be polled to determine if the TouCAN has
entered low-power stop mode. When the TouCAN exits low-power stop mode, the
STOPACK bit is cleared once the TouCAN’s clocks are running.
0 = The TouCAN is not in low-power stop mode and its clocks are running.
1 = The TouCAN has entered low-power stop mode and its clocks are stopped
requests of the same priority. Each module that can generate interrupt requests must be
assigned a unique, non-zero IARB field value.
Stop acknowledge. When the TouCAN is placed in low-power stop mode and shuts down
Interrupt Arbitration ID. The IARB field is used to arbitrate between simultaneous interrupt
Freescale Semiconductor, Inc.
11
0
For More Information On This Product,
CAN 2.0B CONTROLLER MODULE
10
0
ILCAN[2:0]
Go to: www.freescale.com
for more information on entry into and exit from low-power stop mode.
9
0
Rev. 25 June 03
8
0
NOTE
7
0
Description
IVBA[2:0]
6
0
5
0
4
0
3
1
RESERVED
2
1
0xYF F084
MOTOROLA
7.6.2 Low-
1
1
LSB
7-25
0
1