MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 116

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.5.1.4 Data Strobe
4.5.1.5 Read/Write Signal
4.5.1.6 Size Signals
4.5.1.7 Function Codes
MC68F375
REFERENCE MANUAL
Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an
external device to place data on the bus. DS is asserted at the same time as AS during
a read cycle. For a write cycle, DS signals an external device that data on the bus is
valid.
The read/write signal (R/W) determines the direction of the transfer during a bus cycle.
This signal changes state, when required, at the beginning of a bus cycle, and is valid
while AS is asserted. R/W only transitions when a write cycle is preceded by a read
cycle or vice versa. The signal may remain low for two consecutive write cycles.
Size signals (SIZ[1:0]) indicate the number of bytes remaining to be transferred during
an operand cycle. They are valid while AS is asserted.
SIZ1 encoding.
The CPU generates function code signals (FC[2:0]) to indicate the type of activity
occurring on the data or address bus. These signals can be considered address exten-
sions that can be externally decoded to determine which of eight external address
spaces is accessed during a bus cycle. Only supervisor data, supervisor program,
user data, user program, and CPU spaces are defined.
Address space 7 is designated CPU space. CPU space is used for control information
not normally associated with read or write bus cycles. Function codes are valid while
AS is asserted.
Table 4-18
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-17 Size Signal Encoding
SIZ1
0
1
1
0
shows address space encoding.
Go to: www.freescale.com
Rev. 25 June 03
SIZ0
1
0
1
0
Transfer Size
Long word
3 Byte
Word
Byte
Table 4-17
shows SIZ0 and
MOTOROLA
4-34