MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 570

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Num
NOTES:
73
74
75
76
77
78
1. All AC timing is shown with respect to 20% V
2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable t
3. Due to the requirement by the CMFI module, the SCIM2E on this device requires an external clock equal to 2X system fre-
4. Rev B silicon has these pins forced in FAST mode.
5. Pins are set to FAST mode when they are configured as bus and bus control pins. Pins are set to SLOW mode when they
6. These pins have fast and slow rise fall times of 3 and >200, depending on the state of the SLOWE bit in the SCIMMCR.
7. Parameters for an external clock signal applied while the internal PLL is disabled (VDDSYN/MODCLK pin held low during
8. The amount of skew depends on the relative loading of these signals.
9. If multiple chip selects are used, CS width negated applies to the time from the negation of a heavily loaded chip select to the
10. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast cycle reads.
11. Maximum value is equal to (t
12. If the asynchronous setup time requirements are satisfied, the DSACK[1] low to data setup time and DSACK[1] low to BERR
13. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles of the current
14. In the absence of DSACK[1] , BERR is an asynchronous input using the asynchronous setup time.
15. After external RESET negation is detected, a short transition period (approximately 2 t
16. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset is recognized
17. External logic must pull RESET high during this period in order for normal MCU operation to begin.
period is reduced when the duty cycle of the external clock varies. The relationship between external clock input duty cycle
and minimum t
quency to be driven when in external clock mode.
are digital I/O. The SCIM2E has a bit in the MCR to force FAST Mode.
reset). Does not pertain to an external reference clock source while the PLL is enabled (VDDSYN/MODCLK pin held high
during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference signal. If tran-
sitions occur within the correct clock period, rise/fall times and duty cycle are not critical.
assertion of a lightly loaded chip select. The CS width negated between multiple chip selects does not apply to chip selects
being used for synchronous ECLK cycles.
The user is free to use either hold time.
low setup time can be ignored. The data must only satisfy the data-in to clock low setup time for the following clock cycle.
BERR must satisfy only the late BERR low to clock low setup time for the following clock cycle.
operand transfer are complete.
Address access time = (2.5 + WS) t
Chip select access time = (2 + WS) t
Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.
ule drives RESET low for 512 tcyc.
in all cases, RESET must be asserted for at least 590 CLKOUT cycles.
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time
Mode Select Hold Time
RESET Assertion Time
RESET Rise Time
Minimum t
(V
DDH
Xcyc
Xcyc
= 5.0 Vdc
is expressed:
16
,
17
period = minimum t
15
Freescale Semiconductor, Inc.
For More Information On This Product,
cyc
Table E-5 AC Timing (Continued)
10%, V
Characteristic
/ 2) + 25 ns.
ELECTRICAL CHARACTERISTICS
cyc
cyc
DDL
– t
– t
Go to: www.freescale.com
CHAV
XCHL
CLSA
and V
DD
– t
Rev. 25 June 03
/ (50% – external clock input duty cycle tolerance).
– t
and 70% V
DDSYN
DICL
DICL
= 3.3 Vdc
DD
levels unless otherwise noted.
10%, V
SS
= 0 Vdc, T
Symbol
t
t
t
t
t
t
BKHT
RSTA
RSTR
BKST
MSS
MSH
cyc
) elapses, then the Integration Mod-
A
= T
Min
0.25
L
10
—
5
0
2
to T
H
)
1
Max
MOTOROLA
—
—
—
—
—
10
Unit
t
t
t
t
cyc
ns
cyc
ns
cyc
cyc
Xcyc
E-8