MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 164

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Bit(s)
5:4
3:1
0
SPACE
Name
AVEC
IPL
Address space select. Use this option field to select an address space for the chip-select logic.
The CPU32 normally operates in supervisor or user space, but interrupt acknowledge cycles
must take place in CPU space
00 = CPU Space
01 = User Space
10 = Supervisor Space
11 = Supervisor/User Space
Interrupt priority level. When SPACE[1:0] is set for CPU space (0b00), chip-select logic can be
used as an interrupt acknowledge strobe for an external device. During an interrupt acknowl-
edge cycle, the interrupt priority level is driven on address lines ADDR[3:1] is then compared to
the value in IPL[2:0]. If the values match, an interrupt acknowledge strobe will be generated on
the particular chip-select pin, provided other option register conditions are met.
shows IPL[2:0] field encoding.
Autovector enable. This field selects one of two methods of acquiring an interrupt vector during
an interrupt acknowledge cycle. This field is not applicable when SPACE[1:0] = 0b00.
0 = External interrupt vector enabled
1 = Autovector enabled
DSACK[3:0]
Table 4-37 CSOR Bit Descriptions (Continued)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-38 DSACK Field Encoding
Clock Cycles Required
Go to: www.freescale.com
Per Access
Rev. 25 June 03
10
11
12
13
14
15
16
—
3
4
5
6
7
8
9
2
Description
Wait States Inserted
–1 (Fast termination)
External DSACK
Per Access
10
11
12
13
0
1
2
3
4
5
6
7
8
9
Table 4-39
MOTOROLA
4-82