MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 451

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.5.1 32-Bit Coherent Access
13.5.2 DASM Modes of Operation
MC68F375
REFERENCE MANUAL
MODE[3:0]
In the disabled mode (DIS) and in the input modes, the IN bit reflects the state present
on the input pin (after being Schmitt triggered and synchronized). In the output modes
the IN bit reflects the value present at the output of the output flip-flop. The output flip-
flop is used in output modes to hold the logic level applied to the output pin.
The time base bus selector is common to all input and output functions; it connects the
DASM to time base bus A or B and is controlled in software by the bus select bit BSL
in the DASMSIC register.
In the IPWM and IPM modes, 32-bit coherent access of the data registers is sup-
ported. A 32-bit coherent access consists of doing a long word aligned access of data
register A. In this case, register A is accessed first, immediately followed (on the next
cycle) by a register B access. During this time, any flag setting or data transfer from
the hidden B register is deferred until coherent access has ended. When the 32-bit
access has ended, the DASM finishes any pending B action and resumes normal
operation.
The mode of operation of the DASM is determined by the mode select bits MODE[3:0]
in the DASMSIC register (see
0000
0001
0010
0011
0100
0101
1xxx
1. Disable DASM interrupts
2. Change mode
3. Reset the corresponding FLAG bit
To avoid spurious interrupts, and to make sure that the FLAG bit is
set according to the newly selected mode, the following sequence of
operations should be adopted when changing mode:
OPWM
IPWM
OCAB
Mode
OCB
IPM
DIS
IC
Disabled — Input pin is high impedance; IN gives state of the input pin.
Input pulse width measurement — Capture on the leading edge and the trailing edge of
an input pulse.
Input period measurement — Capture two consecutive rising/falling edges.
Input capture — Capture when the designated edge is detected.
Output compare, flag set on B compare — Generate leading and trailing edges of an out-
put pulse and set the flag.
Output compare, flag on A and B compare — Generate leading and trailing edges of an
output pulse and set the flag.
Output pulse width modulation — Generate continuous PWM output with 7, 9, 11, 12,
13, 14, 15 or 16 bits of resolution.
Freescale Semiconductor, Inc.
Table 13-8 DASM Modes of Operation
For More Information On This Product,
CONFIGURABLE TIMER MODULE (CTM9)
Go to: www.freescale.com
Table
Rev. 25 June 03
13-8).
WARNING
Description of mode
MOTOROLA
13-25