MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 367

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

DPTBAR — RAM Array Base Address Register
MISRH — Multiple Input Signature Register High
MISRL — Multiple Input Signature Register Low
RESET:
RESET:
RESET:
9.4.4 MISR High (MISRH) and MISR Low (MISRL)
MC68F375
REFERENCE MANUAL
MSB
MSB
MSB
D31
D15
A23
Bit(s)
15
15
15
0
15:5
0
0
4:1
0
The MISRH and MISRL together contain the 32-bit RAM signature calculated by the
MISC. These registers are read-only and should be read by the host when the MISF
bit in the MCR is set. Note that the naming of the D[31:0] bits represents little-endian
bit encoding.
Exiting TPU3 emulation mode results in the reset of both MISRH and MISRL
A22
D30
D14
14
14
14
0
0
0
RAMDS
A[8:18]
Name
—
A21
D29
D13
13
13
13
0
0
0
RAM array base address. These bits specify the 11 high-order bits (address lines ADDR[8:18]
in little-endian notation) of the 24-bit base address of the RAM array. This allows the array to be
placed on a 8-Kbyte boundary anywhere in the memory map. It is the users responsibility not to
overlap the RAM array memory map with other modules on the chip.
Reserved. (Bits 11:12 represent A[12:11] in DPTRAM implementation that require them.)
RAM disabled. RAMDS is a read-only status bit. The RAM array is disabled after a master reset
since the RAMBAR register may be incorrect. When the array is disabled, it will not respond to
any addresses on the IMB3. Access to the RAM control register block is not affected when the
array is disabled.
RAMDS is cleared by the DPTRAM module when a base address is written to the array address
field of RAMBAR.
RAMDS = 0: RAM enabled
RAMDS = 1: RAM disabled
A20
D28
D12
12
12
12
0
0
0
Freescale Semiconductor, Inc.
D27
D11
A19
11
11
11
0
0
0
For More Information On This Product,
Table 9-3 DPTBAR Bit Settings
A18
D26
D10
DUAL-PORT TPU RAM (DPTRAM)
10
10
10
0
0
0
Go to: www.freescale.com
A17
D25
D9
9
0
9
0
9
0
Rev. 25 June 03
D24
A16
D8
8
0
8
0
8
0
A15
D23
D7
7
0
7
0
7
0
Description
A14
D22
D6
6
0
6
0
6
0
D21
A13
D5
5
0
5
0
5
0
D20
D4
4
0
4
0
4
0
D19
D3
3
Reserved
0
3
0
3
0
D18
D2
2
0
2
0
2
0
0xYF F884
0xYF F886
0xYF F888
MOTOROLA
D17
D1
1
0
1
0
1
0
RAMDS
LSB
LSB
D16
LSB
D0
9-5
0
1
0
0
0
0