MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 412

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

11.4.1 Normal Operation
11.4.1.1 Read/Write
11.4.2 Standby Operation
11.4.2.1 Power Down
11.4.3 RESET Operation
MC68F375
REFERENCE MANUAL
Normal operation is when the SRAM may be accessed via the IMB3 by a bus master
and is being powered by V
may be either read or write.
The SRAM module allows a byte or aligned word read/write in one IMB3 bus cycle.
Long word read/write will require an additional bus cycle. An IMB3 bus cycle requires
2 system clocks.
A separate supply pin is used by the standby SRAM module to maintain the contents
of the SRAM array during a power down phase. The external supply pin of the MCU is
known as V
voltage, either V
TICS. Circuitry within the standby SRAM module will automatically switch between
V
- V
When the SRAM array is powered by the V
array is blocked. Data read from the SRAM array during this condition will not be valid.
Data written to the SRAM may be corrupted if switching occurs during a write opera-
tion. For the module to function correctly as general purpose SRAM, the maximum
value for V
In order to guarantee valid standby SRAM data during power down, external low volt-
age inhibit circuitry, (external to the MCU), must be designed to force the RESET pin
into the active state before V
inhibit a write cycle to the SRAM during power down.
When a synchronous reset occurs, a bus master will be allowed, as a result of internal
synchronization, to complete the current access. Thus, a write bus cycle, byte or word,
that is in progress when a synchronous reset occurs will be completed without error.
During the RESET state, once an in-progress write has been completed, further writes
to the standby SRAM array will be inhibited.
DDL
SWITCH
and V
Byte
Aligned Word
Aligned Long Word
Table 11-4 SRAM Array Read/Write Minimum Access Times
.
STBY
STBY
STBY
. Data in the standby SRAM will be retained down to the lowest supply
. The SRAM module will switch to standby power when V
DDL
V
TYPE
DDL
Freescale Semiconductor, Inc.
STATIC RANDOM ACCESS MEMORY (SRAM)
or V
For More Information On This Product,
.
STBY
DDL
Go to: www.freescale.com
DDL
. The array may be accessed as byte or word. Access
, see
Rev. 25 June 03
drops below its normal limit. This is necessary to
Bus Cycles Required
for Read or Write
APPENDIX E ELECTRICAL CHARACTERIS-
STBY
1
1
2
pin of the MCU, access to the SRAM
Number of System
Clocks
2
2
4
DDL
MOTOROLA
< V
STBY
11-6