MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 120

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6 Bus Operation
MC68F375
REFERENCE MANUAL
Current
NOTES:
Cycle
10
11
12
13
to what states DSACK[1:0] must be driven — either by a chip select or by external cir-
cuitry — to terminate the given bus cycle.
Internal microcontroller modules are typically accessed in two system clock cycles.
Regular external bus cycles use handshaking between the MCU and external periph-
erals to manage transfer size and data. These accesses take a minimum of three
system clock cycles, with no wait states. During regular cycles, wait states can be
inserted as needed by bus control logic. Refer to
information.
Fast-termination cycles, which are two clock external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Refer to
Termination Cycles
timing, as well as chip-select signal timing, is specified in
CHARACTERISTICS. Refer to the
information about each type of bus cycle.
1
2
3
4
5
6
7
8
9
1. Operands in parentheses are ignored by the CPU32 during read cycles.
2. The CPU32 does not support misaligned operand transfers.
3. Three byte transfer cases occur only as a result of an aligned long word to 8-bit port transfer.
Byte to 16-bit port (even)
Long-word to 16-bit port
Long-word to 16-bit port
Byte to 16-bit port (odd)
Three byte to 8-bit port
Byte to 8-bit port (even)
Byte to 8-bit port (odd)
Long-word to 8-bit port
Long-word to 8-bit port
Word to 16-bit port
Word to 16-bit port
Word to 8-bit port
Word to 8-bit port
Transfer Case
(misaligned)
(misaligned)
(misaligned)
(misaligned
(aligned)
(aligned)
(aligned)
(aligned)
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
2
2
Freescale Semiconductor, Inc.
and
For More Information On This Product,
3
Table 4-20 Operand Alignment
4.9 Chip Selects
SIZ1
0
0
0
0
1
1
1
1
0
1
0
1
1
Go to: www.freescale.com
SIZ0
Rev. 25 June 03
1
1
1
1
0
0
0
0
0
0
0
0
1
SCIM Reference Manual (SCIMRM/AD)
ADDR0 DSACK1 DSACK0
0
1
0
1
0
1
0
1
0
1
0
1
1
for more information. Bus control signal
1
1
0
0
1
1
0
0
1
1
0
0
1
4.6.2 Regular Bus Cycle
APPENDIX E ELECTRICAL
0
0
1
1
0
0
1
1
0
0
1
1
0
DATA
[15:8]
(OP0)
(OP0)
(OP0)
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
(OP0)
DATA
(OP0)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
(OP0)
[7:0]
OP0
OP1
OP0
OP1
OP0
MOTOROLA
4.6.3 Fast
1
for more
for more
Cycle
Next
13
—
—
—
—
—
2
1
3
1
7
3
5
4-38