MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 223

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
The software also specifies whether the QADC64 is to perform a single pass through
the queue or is to scan continuously. When a single-scan mode is selected, the soft-
ware selects the queue operating mode and sets the single-scan enable bit. When a
continuous-scan mode is selected, the queue remains active in the selected queue
operating mode after the QADC64 completes each queue scan sequence.
During queue execution, the QADC64 reads each CCW from the active queue and
executes conversions in three stages:
During initial sample, a buffered version of the selected input channel is connected to
the sample capacitor at the output of the sample buffer amplifier.
During the final sample period, the sample buffer amplifier is bypassed, and the mul-
tiplexer input charges the sample capacitor directly. Each CCW specifies a final input
sample time of 2, 4, 8, or 16 QCLK cycles. When an analog-to-digital conversion is
complete, the result is written to the corresponding location in the result word table.
The QADC64 continues to sequentially execute each CCW in the queue until the end
of the queue is detected or a pause bit is found in a CCW.
When the pause bit is set in the current CCW, the QADC64 stops execution of the
queue until a new trigger event occurs. The pause status flag bit is set, which may
cause an interrupt to notify the software that the queue has reached the pause state.
After the trigger event occurs, the paused state ends and the QADC64 continues to
execute each CCW in the queue until another pause is encountered or the end of the
queue is detected.
The following indicate the end-of-queue condition:
When any of the end-of-queue conditions is recognized, a queue completion flag is
set, and if enabled, an interrupt is issued to the software. The following situations pre-
maturely terminate queue execution:
• Expiration of the periodic/interval timer
• External trigger signal
• External gated signal (queue 1 only)
• Initial sample
• Final sample
• Resolution
• The CCW channel field is programmed with 63 (0x3F) to specify the end of the
• The end-of-queue 1 is implied by the beginning of queue 2, which is specified in
• The physical end of the queue RAM space defines the end of either queue.
• Since queue 1 is higher in priority than queue 2, when a trigger event occurs on
queue.
the BQ2 field in QACR2.
queue 1 during queue 2 execution, the execution of queue 2 is suspended by
aborting the execution of the CCW in progress, and the queue 1 execution be-
gins. When queue 1 execution is completed, queue 2 conversions restart with the
first CCW entry in queue 2 or the first CCW of the queue 2 subqueue being exe-
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
MOTOROLA
5-47