MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 386

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

10.4.6 High Voltage Control Register
CMFICTL1 — CMFI High Voltage Control Register 1
MC68F375
REFERENCE MANUAL
MSB
HVS
Bit(s)
13:11
NOTES:
15
9:8
0
15
14
10
RESET:
The high voltage control register is used to control the program and erase operations
of the CMFI array.
1. These fields are NOT locked by SES if the value of the PAWS bits (in CMFITST) is not 0b000.
2. The default state of these bits will be read from the shadow row location 0xC on reset.
14
0
0
SCLKR
CLKPE
Name
HVS
—
—
13
SCLKR
High voltage status. The HVS bit is for status only and writes will have no effect. During a pro-
gram or erase pulse this bit will be a 1 while the pulse is active or during recovery. The BIU will
not acknowledge (IAACKB not asserted) an access to an array location if HVS = 1. While HVS
= 1 SES cannot be changed and the CMFI cannot enter low power clock stop operation. The
program or erase pulse becomes active by setting the EHV bit and is terminated by clearing EHV
or by the pulse width timing control.
The recovery time is the time that the CMFI EEPROM requires to remove the program or erase
voltage from the array or shadow information before switching to another mode of operation. The
recovery time is determined by the system clock range (SCLKR[0:2]) and the PE bit. The recov-
ery time is 48 of the scaled clock periods unless SCLKR = 0 then the recovery time is 128 clocks.
Once master reset is completed HVS shall indicate no program or erase pulse (HVS = 0).
0 = Program or erase pulse is not applied to the CMFI.
1 = Program or erase pulse is applied to the CMFI.
Reserved
System clock range. The SCLKR bits are write protected by the SES bit. Writes to CMFICTL will
not change SCLKR if SES = 1. The first term of the timing control is the clock scaling, R. The
value of R is determined by the system clock range (SCLKR). SCLKR defines the pulse timer’s
base clock using the system clock. The following table should be used to set SCLKR based upon
the system clock frequency. The system clock period is multiplied by the clock scaling value to
generate a 83. 3 ns to 125 ns scaled clock. This scaled clock is used to run the charge pump
submodule and the next functional block of the timing control.
See
Reserved
Clock period exponent. The CLKPE[1:0] bits are write protected by the SES bit. Writes to
CMFICTL will not change CLKPE[1:0] if SES = 1. The second term of the timing control is the
exponential clock multiplier, N. The program pulse number (pulse), clock period exponent
(CLKPE[1:0]) CSC, and PE define the exponent in the 2
nent, N, is defined by the equation:
See
12
U
2
Table 10-11
Table 10-12
1
Freescale Semiconductor, Inc.
11
CDR MoneT FLASH FOR THE IMB3 (CMFI)
For More Information On This Product,
Table 10-9 CMFICTL1 Bit Settings
N = 5 + CLKPE[1:0] + (PE •10)
10
—
0
for SCLKR settings.
for the range of exponents.
Go to: www.freescale.com
9
CLKPE
Rev. 25 June 03
U
2
1
8
—
7
0
Description
6
5
N
multiply of the clock period. The expo-
4
CLKPM
U
3
2
1
2
0xYF F80C
MOTOROLA
1
10-16
LSB
0