MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 280

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

SCCxR1 — SCI Control Register 1
MC68F375
REFERENCE MANUAL
RESET:
Bit(s)
MSB
15
14
13
12
11
10
15
9
8
7
6
5
4
3
2
0
0
LOOPS
LOOPS
WOMS
WAKE
14
Name
0
TCIE
ILIE
RIE
TIE
ILT
RE
PT
PE
TE
—
M
WOM
13
S
0
Reserved
Loop mode
0 = Normal SCI operation, no looping, feedback path disabled.
1 = SCI test operation, looping, feedback path enabled.
Wired-OR mode for SCI Pins
0 = If configured as an output, TXD is a normal CMOS output.
1 = If configured as an output, TXD is an open drain output.
Idle-line detect type. Refer to
0 = Short idle-line detect (start count on first one).
1 = Long idle-line detect (start count on first one after stop bit(s)).
Parity type. Refer to
0 = Even parity.
1 = Odd parity.
Parity enable. Refer to
0 = SCI parity disabled.
1 = SCI parity enabled.
Mode select. Refer to
0 = 10-bit SCI frame.
1 = 11-bit SCI frame.
Wakeup by address mark. Refer to
0 = SCI receiver awakened by idle-line detection.
1 = SCI receiver awakened by address mark (last bit set).
Transmit interrupt enable
0 = SCI TDRE interrupts disabled.
1 = SCI TDRE interrupts enabled.
Transmit complete interrupt enable
0 = SCI TC interrupts disabled.
1 = SCI TC interrupts enabled.
Receiver interrupt enable
0 = SCI RDRF and OR interrupts disabled.
1 = SCI RDRF and OR interrupts enabled.
Idle-line interrupt enable
0 = SCI IDLE interrupts disabled.
1 = SCI IDLE interrupts enabled.
Transmitter enable
0 = SCI transmitter disabled (TXD pin can be used as general-purpose output)
1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter).
Receiver Enable
0 = SCI receiver disabled (RXD pin can be used as general-purpose input).
1 = SCI receiver enabled (RXD pin is dedicated to SCI receiver).
ILT
12
0
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
For More Information On This Product,
PT
11
0
Table 6-24 SCCxR1 Bit Settings
PE
10
0
6.8.7.4 Parity
Go to: www.freescale.com
6.8.7.2 Serial
6.8.7.4 Parity
Rev. 25 June 03
M
9
0
6.8.7.7 Idle-Line
WAKE
8
0
Checking.
6.8.7.8 Receiver
Formats.
Checking.
TIE
Description
7
0
Detection.
TCIE
6
0
Wake-Up.
RIE
5
0
0xYF FC0A, 0xYF FC22
ILIE
4
0
TE
3
0
RE
2
0
MOTOROLA
RWU
1
0
SBK
LSB
6-46
0
0