MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 238

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

6.5 QSMCM Global Registers
MC68F375
REFERENCE MANUAL
NOTES:
cess
S/U
S/U
S/U
S/U
S/U
S/U
Ac-
1. S = Supervisor access only
2. 8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-
3. Note that QRAM offsets have been changed from the original (modular family) QSMCM.
The supervisor-only data space segment contains the QSMCM global registers.
These registers define parameters needed by the QSMCM to integrate with the MCU.
Access to these registers is permitted only when the CPU is operating in supervisor
mode.
Assignable data space can be either restricted to supervisor-only access or unre-
stricted to both supervisor and user accesses. The supervisor (SUPV) bit in the
QSMCM module configuration register (QSMCMMCR) designates the assignable
data space as either supervisor or unrestricted. If SUPV is set, then the space is des-
ignated as supervisor-only space. Access is then permitted only when the CPU is
operating in supervisor mode. If SUPV is clear, both user and supervisor accesses are
permitted. To clear SUPV, the CPU must be in supervisor mode.
The QSMCM assignable data space segment contains the control and status registers
for the QSPI and SCI submodules, as well as the QSPI RAM. All registers and RAM
can be accessed on byte (8-bits), half-word (16-bits), and word (32-bit) boundaries.
Word accesses require two consecutive IMB3 bus cycles.
The QSMCM global registers contain system parameters used by the QSPI and SCI
submodules for interfacing to the CPU and the intermodule bus. The global registers
are listed in
S/U = Supervisor access only or unrestricted user access (assignable data space).
bit boundaries.
1
0xYF FC2C –
0xYF FC4C –
0xYF FC6C –
0xYF FDC0 –
0xYF FD40 –
0xYF FD80 –
0xYF FDBF
0xYF FDDF
0xYF FC4A
0xYF FC6A
0xYF FD3F
0xYF FD7F
Address
Table 6-2 QSMCM Global Registers
Table 6-1 QSMCM Register Map (Continued)
MSB
0
Freescale Semiconductor, Inc.
QUEUED SERIAL MULTI-CHANNEL MODULE
2
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
Transmit Queue Locations (SCTQ)
Receive Queue Locations (SCRQ)
Transmit Data RAM (TRAN.RAM)
Receive Data RAM (REC.RAM)
Command RAM (COMD.RAM)
Reserved
3
3
3
MOTOROLA
LSB
6-4
15