MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 154

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

MC68F375
REFERENCE MANUAL
Because the EBI manages external interrupt requests, the SCIM2E IARB field value
is used for arbitration between internal and external interrupt requests of the same pri-
ority. The reset value of IARB for the SCIM2E is 0b1111, and the reset value of IARB
for all other modules is 0b0000. As noted above, initialization software must assign dif-
ferent values to each IARB field to implement an arbitration scheme.
Although arbitration is intended to deal with simultaneous interrupt requests of the
same priority level, it always take place, even when a single source is requesting ser-
vice. This is important for two reasons: the EBI does not transfer the IACK cycle to the
external bus unless the SCIM2E wins contention, and failure to contend causes the
IACK cycle to be terminated early by bus error.
When arbitration is complete, the winning module must place a vector number on the
data bus and terminate the IACK cycle with DSACK. In the case of external interrupt
requests, the IACK cycle is transferred to the external bus. The device requesting
interrupt service must decode the mask value then respond with a vector number and
generate data and size acknowledge (DSACK) termination signals, or it must assert
AVEC to request an autovector. If the device does not respond in time, the SCIM2E
bus monitor, if enabled, will assert the internal BERR signal and a spurious interrupt
exception will be taken.
Chip-select logic can also be used to generate internal AVEC or DSACK signals in
response to external interrupt requests. Chip-select address match logic functions
only after the SCIM2E has won arbitration, and the resulting IACK cycle is transferred
to the external bus. For this reason, interrupt requests from modules other than the
SCIM2E will never have their IACK cycles terminated by chip-select generated AVEC
or DSACK. Refer to
Cycle Termination
As stated above, all interrupt requests from internal modules have their associated
IACK cycles terminated by DSACK. For this reason, user vectors (instead of autovec-
tors) must always be used for interrupts generated by internal modules.
For periodic timer interrupts, the PIRQL[2:0] field in the periodic interrupt control reg-
ister (PICR) determines PIT priority level. A PIRQL[2:0] value of 0b000 disables PIT
interrupts. By hardware convention, PIT interrupts are serviced before external inter-
rupt service requests or port F edge-detect interrupts requests of the same priority.
External interrupt requests are serviced before requests from the port F edge-detect
logic, as well. Refer to
information.
Do not assign the same arbitration priority to more than one module.
When two or more IARB fields have the same non-zero value, the
CPU32 will interpret multiple vector numbers simultaneously with
unpredictable consequences.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
for more information.
4.9.4.1 Using Chip-Select Signals for Interrupt Acknowledge
For More Information On This Product,
4.4.7 Periodic Interrupt Timer
Go to: www.freescale.com
Rev. 25 June 03
NOTE
and
4.10.4 Port F
MOTOROLA
for more
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