MC68F375BGMZP33 Freescale Semiconductor, MC68F375BGMZP33 Datasheet - Page 124

• Manufacturer Part Number: MC68F375BGMZP33
• Description: IC MPU 32BIT 33MHZ 217-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68F375BGMZP33

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 217-PBGA
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 10 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 16
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.6.4 CPU Space Cycles
MC68F375
REFERENCE MANUAL
Fast termination cycles use internal handshaking signals generated by the chip-select
logic. To initiate a transfer, the MCU drives the address bus and the SIZ[1:0] signals.
When AS, DS, and R/W are valid, a peripheral device either places data on the bus
(read cycle) or latches data from the bus (write cycle). At the appropriate time, chip-
select logic asserts the DSACK[1:0] signals.
The DSACK field in the chip-select option registers determine whether internally gen-
erated DSACK or externally generated DSACK is used. For fast termination cycles,
the fast termination encoding (0b1110) must be used. Refer to
Cycles
The external DSACK lines are always active, regardless of the setting of the DSACK
field in the chip-select option registers. Thus, an external DSACK can always termi-
nate a bus cycle. Holding a DSACK line low will cause essentially all external bus
cycles to be three-cycle (zero wait states) accesses unless the chip-select option reg-
ister specifies fast termination accesses.
To use fast termination, an external device must be fast enough to have data ready
within the specified setup time (for example, by the falling edge of S4). Refer to
APPENDIX E ELECTRICAL CHARACTERISTICS
tion timing.
When a fast termination cycle is issued, DS is asserted for reads but not for writes. The
STRB field in the chip-select option register used must be programmed with the
address strobe encoding to assert the chip-select signal for a fast termination write.
Function code signals FC[2:0] designate which of eight external address spaces is
accessed during a bus cycle. Address space 7 is designated as CPU space. CPU
space is used for control information not normally associated with read or write bus
cycles. Function codes are valid only while AS is asserted. Refer to
Codes
During a CPU space access, ADDR[19:16] are encoded to reflect the type of access
being made. Three encodings are used by the MCU, as shown in
encodings represent breakpoint acknowledge (type 0x0) cycles, low power stop
broadcast (type 0x3) cycles, and interrupt acknowledge (type 0xF) cycles. Type 0x0
and type 0x3 cycles are discussed in the following paragraphs. Refer to
for information about interrupt acknowledge bus cycles.
for more information on codes and encoding.
for information about fast termination setup.
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Rev. 25 June 03
for information about fast termina-
4.6.3 Fast Termination
Figure
4.5.1.7 Function
4.8 Interrupts
4-13. These
MOTOROLA
4-42